from nmigen_boards.test.blinky import Blinky
from icarusversa import IcarusVersaPlatform
# Clock-Reset Generator (works for all ECP5 platforms)
-from crg import ECPIX5CRG
+from ecp5_crg import ECP5CRG
from arty_crg import ArtyA7CRG
import sys
# set up clock request generator
if fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim', 'ulx3s']:
- self.crg = ECPIX5CRG(clk_freq)
+ self.crg = ECP5CRG(clk_freq)
if fpga in ['arty_a7']:
self.crg = ArtyA7CRG(clk_freq)
else:
platform = None
+ print ("platform", fpga, firmware, platform)
+
# set clock frequency
clk_freq = 70e6
if fpga == 'sim':
clk_freq = 100e6
+ if fpga == 'isim':
+ clk_freq = 50e6 # below 50 mhz, stops DRAM being enabled
if fpga == 'versa_ecp5':
clk_freq = 50e6 # crank right down to test hyperram
if fpga == 'versa_ecp5_85':
if fpga == 'arty_a7':
clk_freq = 50e6
if fpga == 'ulx3s':
- clk_freq = 12.5e6
+ clk_freq = 40.0e6
# select a firmware address
fw_addr = None
# Get HyperRAM pins
hyperram_pins = None
- if platform is None or platform in ['isim']:
+ if platform is None:
hyperram_pins = HyperRAMPads()
+ elif fpga in ['isim']:
+ hyperram_ios = HyperRAMResource(0, cs_n="B11",
+ dq="D4 D3 F4 F3 G2 H2 D2 E2",
+ rwds="U13", rst_n="T13", ck_p="V10",
+ # ck_n="D12" - for later (DDR)
+ attrs=Attrs(IOSTANDARD="LVCMOS33"))
+ platform.add_resources(hyperram_ios)
+ hyperram_pins = platform.request("hyperram")
+ print ("isim a7 hyperram", hyperram_ios)
# Digilent Arty A7-100t
elif platform is not None and fpga in ['arty_a7']:
hyperram_ios = HyperRAMResource(0, cs_n="B11",
platform.add_resources(hyperram_ios)
hyperram_pins = platform.request("hyperram")
print ("versa ecp5 hyperram", hyperram_ios)
+ print ("hyperram pins", hyperram_pins)
# set up the SOC
soc = DDR3SoC(fpga=fpga, dram_cls=dram_cls,