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add FPGA argument to DDR3SoC
[ls2.git]
/
src
/
ls2.py
diff --git
a/src/ls2.py
b/src/ls2.py
index 54d4f4d9f7308adee97c2ffcb8723d2d364001c7..7fe9ca3af29cef4c7e94f12f7ab3fc819d87a8ce 100644
(file)
--- a/
src/ls2.py
+++ b/
src/ls2.py
@@
-297,7
+297,7
@@
if __name__ == "__main__":
"odt":4, "ras":4, "cas":4, "we":4})
# set up the SOC
- soc = DDR3SoC(dram_cls,
+ soc = DDR3SoC(
fpga,
dram_cls,
ddrphy_addr=0xff000000, # DRAM firmware init base
dramcore_addr=0x80000000,
ddr_addr=0x10000000,