package sifive.blocks.devices.gpio
import Chisel._
-import diplomacy.LazyModule
-import rocketchip.{TopNetwork,TopNetworkModule}
-import uncore.tilelink2.TLFragmenter
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
+import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
+import freechips.rocketchip.util.HeterogeneousBag
-trait PeripheryGPIO {
- this: TopNetwork { val gpioConfig: GPIOConfig } =>
- val gpio = LazyModule(new TLGPIO(gpioConfig))
- gpio.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
- intBus.intnode := gpio.intnode
+case object PeripheryGPIOKey extends Field[Seq[GPIOParams]]
+
+trait HasPeripheryGPIO extends HasPeripheryBus with HasInterruptBus {
+ val gpioParams = p(PeripheryGPIOKey)
+ val gpios = gpioParams map { params =>
+ val gpio = LazyModule(new TLGPIO(pbus.beatBytes, params))
+ gpio.node := pbus.toVariableWidthSlaves
+ ibus.fromSync := gpio.intnode
+ gpio
+ }
}
-trait PeripheryGPIOBundle {
- this: { val gpioConfig: GPIOConfig } =>
- val gpio = new GPIOPortIO(gpioConfig)
+trait HasPeripheryGPIOBundle {
+ val gpio: HeterogeneousBag[GPIOPortIO]
}
-trait PeripheryGPIOModule {
- this: TopNetworkModule {
- val gpioConfig: GPIOConfig
- val outer: PeripheryGPIO
- val io: PeripheryGPIOBundle
- } =>
- io.gpio <> outer.gpio.module.io.port
+trait HasPeripheryGPIOModuleImp extends LazyMultiIOModuleImp with HasPeripheryGPIOBundle {
+ val outer: HasPeripheryGPIO
+ val gpio = IO(HeterogeneousBag(outer.gpioParams.map(new GPIOPortIO(_))))
+
+ (gpio zip outer.gpios) foreach { case (io, device) =>
+ io <> device.module.io.port
+ }
}