endmodule
"""
-def latchregister(m, incoming, outgoing, settrue):
- reg = Signal.like(incoming) # make register same as input. reset is OK.
+def latchregister(m, incoming, outgoing, settrue, name=None):
+ reg = Signal.like(incoming, name=name) # make reg same as input. reset OK.
with m.If(settrue):
m.d.sync += reg.eq(incoming) # latch input into register
m.d.comb += outgoing.eq(incoming) # return input (combinatorial)