power_insn: support verbose disassembly mode

[openpower-isa.git] / src / openpower / consts.py

diff --git a/src/openpower/consts.py b/src/openpower/consts.py
index 4ec670eba8dbc1110808a85877970c560c54e51e..8f0ea054682f3fcb24ce08ae8287c0578530e11a 100644 (file)
--- a/src/openpower/consts.py
+++ b/src/openpower/consts.py
@@ -201,6 +201,13 @@ class EXTRA2b(_Const):
 EXTRA2_SIZE = 9
 EXTRA2 = _ConstLE("EXTRA2", names=EXTRA2b, msb=EXTRA2_SIZE-1)
 
+# sigh, make these convenience-modifications afterwards (aliases)
+# see RM-2P-1S1D-PU in https://libre-soc.org/openpower/sv/svp64
+EXTRA2b.PACK_en   = EXTRA2b.IDX2_VEC
+EXTRA2b.UNPACK_en = EXTRA2b.IDX2_MSB
+EXTRA2.PACK_en    = EXTRA2.IDX2_VEC
+EXTRA2.UNPACK_en  = EXTRA2.IDX2_MSB
+
 
 # EXTRA field, with EXTRA3 subfield encoding
 class EXTRA3:
@@ -234,7 +241,9 @@ class SVP64MODEb(_Const):
     # mode bits
     MOD2_MSB = 0
     MOD2_LSB = 1
-    LDST_SHIFT = 2 # set =1 for shift mode
+    # pack detection (TODO, CR-ops needs one of these too)
+    LDST_PACK = 2 # set =1 for LD/ST-immediate Pack mode
+    ARITH_PACK = 4 # set =1 for Arithmetic Pack mode
     # when predicate not set: 0=ignore/skip 1=zero
     DZ = 3  # for destination
     SZ = 4  # for source
@@ -331,3 +340,7 @@ class XERRegsEnum:
     CA=1 # CA and CA32
     OV=2 # OV and OV32
     N_REGS = 3 # maximum number of regs
+
+
+if __name__ == '__main__':
+    print ("EXTRA2 pack", EXTRA2.PACK_en, EXTRA2.PACK_en.value)