# mode bits
MOD2_MSB = 0
MOD2_LSB = 1
+ LDST_SHIFT = 2 # set =1 for shift mode
# when predicate not set: 0=ignore/skip 1=zero
DZ = 3 # for destination
SZ = 4 # for source
+ # for branch-conditional
+ BC_SNZ = 3 # for branch-conditional mode
+ BC_VLI = 2 # for VL include/exclude on VLSET mode
+ BC_VLSET = 1 # VLSET mode
+ BC_SVSTEP = 0 # svstep mode
# reduce mode
REDUCE = 2 # 0=normal predication 1=reduce mode
+ PARALLEL = 3 # 1=parallel reduce, 0=scalar reduce
SVM = 3 # subvector reduce mode 0=independent 1=horizontal
CRM = 4 # CR mode on reduce (Rc=1) 0=some 1=all
+ RG = 4 # Reverse-gear on reduce
# saturation mode
N = 2 # saturation signed mode 0=signed 1=unsigned
# ffirst and predicate result modes
CR_LSB = 4
RC1 = 4 # update CR as if Rc=1 (when Rc=0)
# LD immediate els (element-stride) locations, depending on mode
- ELS_NORMAL = 2
+ ELS_NORMAL = 4
ELS_FFIRST_PRED = 3
ELS_SAT = 4
# BO bits
XER = 5 # non-XER bits
DEC = 6
TB = 7
- N_REGS = 8 # maximum number of regs
+ SVSRR0 = 8
+ N_REGS = 9 # maximum number of regs
# XER Regfile
class XERRegsEnum: