allow ignoring FPSCR in tests

[openpower-isa.git] / src / openpower / consts.py

diff --git a/src/openpower/consts.py b/src/openpower/consts.py
index 3a5e2c8e3ad29e499e07f3cda6ca94d93ea4c458..f31ab5611bdb7eaa09267a138eb4e5f6e5e2b0ac 100644 (file)
--- a/src/openpower/consts.py
+++ b/src/openpower/consts.py
@@ -242,13 +242,11 @@ class SVP64MODEb(_Const):
     MOD2_MSB = 0
     MOD2_LSB = 1
     MOD3 = 3
-    # pack detection (TODO, CR-ops needs one of these too)
-    LDST_PACK = 2 # set =1 for LD/ST-immediate Pack mode
-    ARITH_PACK = 4 # set =1 for Arithmetic Pack mode
+    SEA = 2
     # when predicate not set: 0=ignore/skip 1=zero
     DZ = 3  # for destination
     SZ = 4  # for source
-    ZZ = 3  # for both sz/dz, on all but CR-ops
+    ZZ = 3  # for both sz/dz, on all but CR-ops, which, whoops, is RM bit 6.
     # for branch-conditional
     BC_SNZ = 3  # for branch-conditional mode
     BC_VLI = 2  # for VL include/exclude on VLSET mode
@@ -256,7 +254,6 @@ class SVP64MODEb(_Const):
     BC_CTRTEST = 0 # CTR-test mode
     # reduce mode
     REDUCE = 2  # 0=normal predication 1=reduce mode
-    SVM = 3  # subvector reduce mode 0=independent 1=horizontal
     CRM = 4  # CR mode on reduce (Rc=1) 0=some 1=all
     RG = 4   # Reverse-gear on reduce
     # saturation mode
@@ -265,11 +262,19 @@ class SVP64MODEb(_Const):
     INV = 2  # invert CR sense 0=set 1=unset
     CR_MSB = 3  # CR bit to update (with Rc=1)
     CR_LSB = 4
+    VLI = 3
     RC1 = 4  # update CR as if Rc=1 (when Rc=0)
     # LD immediate els (element-stride) locations, depending on mode
     ELS_NORMAL = 4
     ELS_FFIRST_PRED = 3
     ELS_SAT = 4
+    LDI_POST = 2 # LD-Immediate Post/FF Mode
+    LDI_PI = 3 # LD-Immediate Post-Increment
+    LDI_FF = 4 # LD-Immediate Fault-First
+    # LDST Indexed
+    LDIDX_ELS = 0 # Indexed element-strided
+    # LDST VLI for ffirst is in bit 0
+    LDST_VLI = 0
     # BO bits
     BO_MSB = 2
     BO_LSB = 4