move SVP64 RM mode decoder into PowerDecodeSubset

[openpower-isa.git] / src / openpower / decoder / decode2execute1.py

diff --git a/src/openpower/decoder/decode2execute1.py b/src/openpower/decoder/decode2execute1.py
index 6333dcdf87641405b68fc438761cf222e7755d34..628f2d475047a2e2310750b5c2dc431d0a768375 100644 (file)
--- a/src/openpower/decoder/decode2execute1.py
+++ b/src/openpower/decoder/decode2execute1.py
@@ -5,10 +5,11 @@ based on Anton Blanchard microwatt decode2.vhdl
 """
 from nmigen import Signal, Record
 from nmutil.iocontrol import RecordObject
-from soc.decoder.power_enums import (MicrOp, CryIn, Function,
+from openpower.decoder.power_enums import (MicrOp, CryIn, Function,
                                      SPRfull, SPRreduced, LDSTMode)
-from soc.consts import TT
-from soc.experiment.mem_types import LDSTException
+from openpower.consts import TT
+from openpower.exceptions import LDSTException
+from openpower.decoder.power_svp64_rm import sv_input_record_layout
 
 
 class Data(Record):
@@ -37,11 +38,13 @@ class IssuerDecode2ToOperand(RecordObject):
 
     def __init__(self, name=None):
 
-        RecordObject.__init__(self, name=name)
+        RecordObject.__init__(self, layout=sv_input_record_layout,
+                                    name=name)
 
         # current "state" (TODO: this in its own Record)
         self.msr = Signal(64, reset_less=True)
         self.cia = Signal(64, reset_less=True)
+        self.svstate = Signal(32, reset_less=True)
 
         # instruction, type and decoded information
         self.insn = Signal(32, reset_less=True) # original instruction
@@ -111,10 +114,13 @@ class Decode2ToExecute1Type(RecordObject):
         self.xer_in = Signal(3, reset_less=True)   # xer might be read
         self.xer_out = Signal(reset_less=True)  # xer might be written
 
+        # for the FAST regs (SRR1, SRR2, SVSRR0, CTR, LR etc.)
         self.read_fast1 = Data(3, name="fast1")
         self.read_fast2 = Data(3, name="fast2")
+        self.read_fast3 = Data(3, name="fast3")   # really only for SVSRR0
         self.write_fast1 = Data(3, name="fasto1")
         self.write_fast2 = Data(3, name="fasto2")
+        self.write_fast3 = Data(3, name="fasto3") # likewise
 
         self.read_cr1 = Data(7, name="cr_in1")
         self.read_cr2 = Data(7, name="cr_in2")