self.rc = Data(1, "rc")
self.oe = Data(1, "oe")
self.input_carry = Signal(CryIn, reset_less=True)
+ self.output_carry = Signal(reset_less=True)
self.traptype = Signal(TT.size, reset_less=True) # trap main_stage.py
self.ldst_exc = LDSTException("exc")
self.trapaddr = Signal(13, reset_less=True)
self.is_signed = Signal(reset_less=True)
self.data_len = Signal(4, reset_less=True) # bytes
self.byte_reverse = Signal(reset_less=True)
+ self.reserve = Signal(reset_less=True) # atomic update ldarx/stdcx etc
self.sign_extend = Signal(reset_less=True)# do we need this?
self.ldst_mode = Signal(LDSTMode, reset_less=True) # LD/ST mode
self.write_cr0 = Signal(reset_less=True)
self.xer_out = Signal(reset_less=True) # xer might be written
# for the FAST regs (SRR1, SRR2, SVSRR0, CTR, LR etc.)
- self.read_fast1 = Data(3, name="fast1")
- self.read_fast2 = Data(3, name="fast2")
- self.read_fast3 = Data(3, name="fast3") # really only for SVSRR0
- self.write_fast1 = Data(3, name="fasto1")
- self.write_fast2 = Data(3, name="fasto2")
- self.write_fast3 = Data(3, name="fasto3") # likewise
+ self.read_fast1 = Data(4, name="fast1")
+ self.read_fast2 = Data(4, name="fast2")
+ self.read_fast3 = Data(4, name="fast3") # really only for SVSRR0
+ self.write_fast1 = Data(4, name="fasto1")
+ self.write_fast2 = Data(4, name="fasto2")
+ self.write_fast3 = Data(4, name="fasto3") # likewise
+ # and STATE regs (DEC, TB)
+ self.read_state1 = Data(3, name="state1") # really only for DEC/TB
+ self.write_state1 = Data(3, name="state1")
self.read_cr1 = Data(7, name="cr_in1")
self.read_cr2 = Data(7, name="cr_in2")