power_insn: refactor opcode matching

[openpower-isa.git] / src / openpower / decoder / decode2execute1.py

diff --git a/src/openpower/decoder/decode2execute1.py b/src/openpower/decoder/decode2execute1.py
index d0f37d2e062a242bc2bfdb9ba03cbb5cce81ad5e..767d84967ff40b6e86ae4d89ded535ad5998427a 100644 (file)
--- a/src/openpower/decoder/decode2execute1.py
+++ b/src/openpower/decoder/decode2execute1.py
@@ -120,12 +120,15 @@ class Decode2ToExecute1Type(RecordObject):
         self.xer_out = Signal(reset_less=True)  # xer might be written
 
         # for the FAST regs (SRR1, SRR2, SVSRR0, CTR, LR etc.)
-        self.read_fast1 = Data(3, name="fast1")
-        self.read_fast2 = Data(3, name="fast2")
-        self.read_fast3 = Data(3, name="fast3")   # really only for SVSRR0
-        self.write_fast1 = Data(3, name="fasto1")
-        self.write_fast2 = Data(3, name="fasto2")
-        self.write_fast3 = Data(3, name="fasto3") # likewise
+        self.read_fast1 = Data(4, name="fast1")
+        self.read_fast2 = Data(4, name="fast2")
+        self.read_fast3 = Data(4, name="fast3")   # really only for SVSRR0
+        self.write_fast1 = Data(4, name="fasto1")
+        self.write_fast2 = Data(4, name="fasto2")
+        self.write_fast3 = Data(4, name="fasto3") # likewise
+        # and STATE regs (DEC, TB)
+        self.read_state1 = Data(3, name="state1")  # really only for DEC/TB
+        self.write_state1 = Data(3, name="state1")
 
         self.read_cr1 = Data(7, name="cr_in1")
         self.read_cr2 = Data(7, name="cr_in2")