add OP_FETCH_FAILED micro-op

[openpower-isa.git] / src / openpower / decoder / decode2execute1.py

diff --git a/src/openpower/decoder/decode2execute1.py b/src/openpower/decoder/decode2execute1.py
index 1d4808383be8595580a5342793a52dba92828557..e7deff5b2608cc69769eb321ac1d621a3001ffc7 100644 (file)
--- a/src/openpower/decoder/decode2execute1.py
+++ b/src/openpower/decoder/decode2execute1.py
@@ -47,7 +47,7 @@ class IssuerDecode2ToOperand(RecordObject):
         # current "state" (TODO: this in its own Record)
         self.msr = Signal(64, reset_less=True)
         self.cia = Signal(64, reset_less=True)
-        self.svstate = Signal(32, reset_less=True)
+        self.svstate = Signal(64, reset_less=True)
 
         # instruction, type and decoded information
         self.insn = Signal(32, reset_less=True) # original instruction
@@ -57,6 +57,7 @@ class IssuerDecode2ToOperand(RecordObject):
         self.rc = Data(1, "rc")
         self.oe = Data(1, "oe")
         self.input_carry = Signal(CryIn, reset_less=True)
+        self.output_carry = Signal(reset_less=True)
         self.traptype  = Signal(TT.size, reset_less=True) # trap main_stage.py
         self.ldst_exc  = LDSTException("exc")
         self.trapaddr  = Signal(13, reset_less=True)
@@ -127,7 +128,7 @@ class Decode2ToExecute1Type(RecordObject):
 
         self.read_cr1 = Data(7, name="cr_in1")
         self.read_cr2 = Data(7, name="cr_in2")
-        self.read_cr3 = Data(7, name="cr_in2")
+        self.read_cr3 = Data(7, name="cr_in3")
         self.write_cr = Data(7, name="cr_out")
 
         # decode operand data