insns, MicrOp, In1Sel, In2Sel, In3Sel,
OutSel, CROutSel, LDSTMode,
SVP64RMMode, SVP64PredMode,
- SVP64PredInt, SVP64PredCR)
+ SVP64PredInt, SVP64PredCR,
+ SVP64LDSTmode)
from openpower.decoder.power_enums import SVPtype
-from openpower.decoder.helpers import exts, gtu, ltu, undefined
+from openpower.decoder.helpers import (exts, gtu, ltu, undefined, bitrev)
from openpower.consts import PIb, MSRb # big-endian (PowerISA versions)
from openpower.consts import SVP64CROffs
from openpower.decoder.power_svp64 import SVP64RM, decode_extra
from openpower.decoder.isa.radixmmu import RADIX
from openpower.decoder.isa.mem import Mem, swap_order, MemException
+from openpower.decoder.isa.svshape import SVSHAPE
from openpower.util import log
"TAR": 0,
"MSR": 0,
"SVSTATE": 0,
+ "SVSHAPE0": 0,
+ "SVSHAPE1": 0,
+ "SVSHAPE2": 0,
+ "SVSHAPE3": 0,
"CA": 0,
"CA32": 0,
self.sd = decoder
self.isacaller = isacaller
self.svstate = svstate
- for i in range(32):
+ for i in range(len(regfile)):
self[i] = SelectableInt(regfile[i], 64)
def __call__(self, ridx):
+ if isinstance(ridx, SelectableInt):
+ ridx = ridx.value
return self[ridx]
def set_form(self, form):
self.form = form
+ def __setitem__(self, rnum, value):
+ # rnum = rnum.value # only SelectableInt allowed
+ log("GPR setitem", rnum, value)
+ if isinstance(rnum, SelectableInt):
+ rnum = rnum.value
+ dict.__setitem__(self, rnum, value)
+
def getz(self, rnum):
# rnum = rnum.value # only SelectableInt allowed
log("GPR getzero?", rnum)
""" XXX currently not used
"""
rnum = self._get_regnum(attr)
- offs = self.svstate.srcstep
- log("GPR getitem", attr, rnum, "srcoffs", offs)
+ log("GPR getitem", attr, rnum)
return self.regfile[rnum]
def dump(self, printout=True):
for j in range(8):
s.append("%08x" % res[i+j])
s = ' '.join(s)
- log("reg", "%2d" % i, s)
+ print("reg", "%2d" % i, s)
return res
def dump(self, printout=True):
res = []
keys = list(self.keys())
- keys.sort()
+ #keys.sort()
for k in keys:
sprname = spr_dict.get(k, None)
if sprname is None:
res.append((sprname, self[k].value))
if printout:
for sprname, value in res:
- log(" ", sprname, hex(value))
+ print(" ", sprname, hex(value))
return res
return mask
+# TODO, really should just be using PowerDecoder2
def get_pdecode_idx_in(dec2, name):
op = dec2.dec.op
in1_sel = yield op.in1_sel
in3, in3_isvec)
log ("get_pdecode_idx_in FRS in3", name, in3_sel, In3Sel.FRS.value,
in3, in3_isvec)
+ log ("get_pdecode_idx_in FRB in2", name, in2_sel, In2Sel.FRB.value,
+ in2, in2_isvec)
log ("get_pdecode_idx_in FRC in3", name, in3_sel, In3Sel.FRC.value,
in3, in3_isvec)
# identify which regnames map to in1/2/3
return None, False
+# TODO, really should just be using PowerDecoder2
def get_pdecode_cr_out(dec2, name):
op = dec2.dec.op
out_sel = yield op.cr_out
return None, False
+# TODO, really should just be using PowerDecoder2
def get_pdecode_idx_out(dec2, name):
op = dec2.dec.op
out_sel = yield op.out_sel
return out, o_isvec
elif name == 'RT':
log ("get_pdecode_idx_out", out_sel, OutSel.RT.value,
- OutSel.RT_OR_ZERO.value, out, o_isvec)
+ OutSel.RT_OR_ZERO.value, out, o_isvec,
+ dec2.dec.RT)
if out_sel == OutSel.RT.value:
return out, o_isvec
elif name == 'FRA':
return None, False
+# TODO, really should just be using PowerDecoder2
def get_pdecode_idx_out2(dec2, name):
# check first if register is activated for write
- out_ok = yield dec2.e.write_ea.ok
- if not out_ok:
- return None, False
-
op = dec2.dec.op
out_sel = yield op.out_sel
out = yield dec2.e.write_ea.data
o_isvec = yield dec2.o2_isvec
- log ("get_pdecode_idx_out2", name, out_sel, out, o_isvec)
+ out_ok = yield dec2.e.write_ea.ok
+ log ("get_pdecode_idx_out2", name, out_sel, out, out_ok, o_isvec)
+ if not out_ok:
+ return None, False
+
if name == 'RA':
if hasattr(op, "upd"):
# update mode LD/ST uses read-reg A also as an output
out, o_isvec)
if upd == LDSTMode.update.value:
return out, o_isvec
+ if name == 'FRS':
+ int_op = yield dec2.dec.op.internal_op
+ fft_en = yield dec2.use_svp64_fft
+ #if int_op == MicrOp.OP_FP_MADD.value and fft_en:
+ if fft_en:
+ log ("get_pdecode_idx_out2", out_sel, OutSel.FRS.value,
+ out, o_isvec)
+ return out, o_isvec
return None, False
for i, code in enumerate(disassembly):
self.disassembly[i*4 + disasm_start] = code
- # set up registers, instruction memory, data memory, PC, SPRs, MSR
+ # set up registers, instruction memory, data memory, PC, SPRs, MSR, CR
self.svp64rm = SVP64RM()
if initial_svstate is None:
initial_svstate = 0
if isinstance(initial_svstate, int):
initial_svstate = SVP64State(initial_svstate)
+ # SVSTATE, MSR and PC
self.svstate = initial_svstate
+ self.msr = SelectableInt(initial_msr, 64) # underlying reg
+ self.pc = PC()
+ # GPR FPR SPR registers
self.gpr = GPR(decoder2, self, self.svstate, regfile)
self.fpr = GPR(decoder2, self, self.svstate, fpregfile)
self.spr = SPR(decoder2, initial_sprs) # initialise SPRs before MMU
+
+ # set up 4 dummy SVSHAPEs if they aren't already set up
+ for i in range(4):
+ sname = 'SVSHAPE%d' % i
+ if sname not in self.spr:
+ self.spr[sname] = SVSHAPE(0)
+ else:
+ # make sure it's an SVSHAPE
+ val = self.spr[sname].value
+ self.spr[sname] = SVSHAPE(val)
+ self.last_op_svshape = False
+
+ # "raw" memory
self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
# MMU mode, redirect underlying Mem through RADIX
- self.msr = SelectableInt(initial_msr, 64) # underlying reg
if mmu:
self.mem = RADIX(self.mem, self)
if icachemmu:
self.imem = RADIX(self.imem, self)
- self.pc = PC()
# TODO, needed here:
# FPR (same as GPR except for FP nums)
'NIA': self.pc.NIA,
'CIA': self.pc.CIA,
'SVSTATE': self.svstate.spr,
+ 'SVSHAPE0': self.spr['SVSHAPE0'],
+ 'SVSHAPE1': self.spr['SVSHAPE1'],
+ 'SVSHAPE2': self.spr['SVSHAPE2'],
+ 'SVSHAPE3': self.spr['SVSHAPE3'],
'CR': self.cr,
'MSR': self.msr,
'undefined': undefined,
self.namespace['CA'] = self.spr['XER'][XER_bits['CA']].value
self.namespace['CA32'] = self.spr['XER'][XER_bits['CA32']].value
+ # add some SVSTATE convenience variables
+ vl = self.svstate.vl.asint(msb0=True)
+ srcstep = self.svstate.srcstep.asint(msb0=True)
+ self.namespace['VL'] = vl
+ self.namespace['srcstep'] = srcstep
+
def handle_carry_(self, inputs, outputs, already_done):
inv_a = yield self.dec2.e.do.invert_in
if inv_a:
self.namespace['NIA'] = SelectableInt(pc_val, 64)
self.pc.update(self.namespace, self.is_svp64_mode)
- def setup_one(self):
- """set up one instruction
+ def get_next_insn(self):
+ """check instruction
"""
if self.respect_pc:
pc = self.pc.CIA.value
else:
pc = self.fake_pc
- self._pc = pc
ins = self.imem.ld(pc, 4, False, True, instr_fetch=True)
if ins is None:
raise KeyError("no instruction at 0x%x" % pc)
+ return pc, ins
+
+ def setup_one(self):
+ """set up one instruction
+ """
+ pc, insn = self.get_next_insn()
+ yield from self.setup_next_insn(pc, insn)
+
+ def setup_next_insn(self, pc, ins):
+ """set up next instruction
+ """
+ self._pc = pc
log("setup: 0x%x 0x%x %s" % (pc, ins & 0xffffffff, bin(ins)))
log("CIA NIA", self.respect_pc, self.pc.CIA.value, self.pc.NIA.value)
pfx.insn[7].value == 0b1 and
pfx.insn[9].value == 0b1)
self.pc.update_nia(self.is_svp64_mode)
+ yield self.dec2.is_svp64_mode.eq(self.is_svp64_mode) # set SVP64 decode
self.namespace['NIA'] = self.pc.NIA
self.namespace['SVSTATE'] = self.svstate.spr
if not self.is_svp64_mode:
def call(self, name):
"""call(opcode) - the primary execution point for instructions
"""
+ self.last_st_addr = None # reset the last known store address
+ self.last_ld_addr = None # etc.
+
name = name.strip() # remove spaces if not already done so
if self.halted:
log("halted - not executing", name)
illegal = False
name = 'setvl'
+ # and svremap not being supported by binutils (.long)
+ if asmop.startswith('svremap'):
+ illegal = False
+ name = 'svremap'
+
+ # sigh also deal with ffmadds not being supported by binutils (.long)
+ if asmop == 'ffmadds':
+ illegal = False
+ name = 'ffmadds'
+
+ # and ffadds not being supported by binutils (.long)
+ if asmop == 'ffadds':
+ illegal = False
+ name = 'ffadds'
+
if illegal:
print("illegal", name, asmop)
self.call_trap(0x700, PIb.ILLEG)
(name, asmop, self.pc.CIA.value))
return
+ # this is for setvl "Vertical" mode: if set true,
+ # srcstep/dststep is explicitly advanced
+ self.allow_next_step_inc = False
+
# nop has to be supported, we could let the actual op calculate
# but PowerDecoder has a pattern for nop
if name is 'nop':
dest_cr, src_cr, src_byname, dest_byname = False, False, {}, {}
log ("sv rm", sv_rm, dest_cr, src_cr, src_byname, dest_byname)
- # get SVSTATE VL (oh and print out some debug stuff)
+ # see if srcstep/dststep need skipping over masked-out predicate bits
if self.is_svp64_mode:
- vl = self.svstate.vl.asint(msb0=True)
- srcstep = self.svstate.srcstep.asint(msb0=True)
- dststep = self.svstate.dststep.asint(msb0=True)
- sv_a_nz = yield self.dec2.sv_a_nz
- in1 = yield self.dec2.e.read_reg1.data
- log ("SVP64: VL, srcstep, dststep, sv_a_nz, in1",
- vl, srcstep, dststep, sv_a_nz, in1)
-
- # get predicate mask
- srcmask = dstmask = 0xffff_ffff_ffff_ffff
- if self.is_svp64_mode:
- pmode = yield self.dec2.rm_dec.predmode
- sv_ptype = yield self.dec2.dec.op.SV_Ptype
- srcpred = yield self.dec2.rm_dec.srcpred
- dstpred = yield self.dec2.rm_dec.dstpred
- pred_src_zero = yield self.dec2.rm_dec.pred_sz
- pred_dst_zero = yield self.dec2.rm_dec.pred_dz
- if pmode == SVP64PredMode.INT.value:
- srcmask = dstmask = get_predint(self.gpr, dstpred)
- if sv_ptype == SVPtype.P2.value:
- srcmask = get_predint(self.gpr, srcpred)
- elif pmode == SVP64PredMode.CR.value:
- srcmask = dstmask = get_predcr(self.crl, dstpred, vl)
- if sv_ptype == SVPtype.P2.value:
- srcmask = get_predcr(self.crl, srcpred, vl)
- log (" pmode", pmode)
- log (" ptype", sv_ptype)
- log (" srcpred", bin(srcpred))
- log (" dstpred", bin(dstpred))
- log (" srcmask", bin(srcmask))
- log (" dstmask", bin(dstmask))
- log (" pred_sz", bin(pred_src_zero))
- log (" pred_dz", bin(pred_dst_zero))
-
- # okaaay, so here we simply advance srcstep (TODO dststep)
- # until the predicate mask has a "1" bit... or we run out of VL
- # let srcstep==VL be the indicator to move to next instruction
- if not pred_src_zero:
- while (((1<<srcstep) & srcmask) == 0) and (srcstep != vl):
- log (" skip", bin(1<<srcstep))
- srcstep += 1
- # same for dststep
- if not pred_dst_zero:
- while (((1<<dststep) & dstmask) == 0) and (dststep != vl):
- log (" skip", bin(1<<dststep))
- dststep += 1
-
- # now work out if the relevant mask bits require zeroing
- if pred_dst_zero:
- pred_dst_zero = ((1<<dststep) & dstmask) == 0
- if pred_src_zero:
- pred_src_zero = ((1<<srcstep) & srcmask) == 0
-
- # update SVSTATE with new srcstep
- self.svstate.srcstep[0:7] = srcstep
- self.svstate.dststep[0:7] = dststep
- self.namespace['SVSTATE'] = self.svstate.spr
- yield self.dec2.state.svstate.eq(self.svstate.spr.value)
- yield Settle() # let decoder update
- srcstep = self.svstate.srcstep.asint(msb0=True)
- dststep = self.svstate.dststep.asint(msb0=True)
- log (" srcstep", srcstep)
- log (" dststep", dststep)
-
- # check if end reached (we let srcstep overrun, above)
- # nothing needs doing (TODO zeroing): just do next instruction
- if srcstep == vl or dststep == vl:
+ yield from self.svstate_pre_inc()
+ pre = yield from self.update_new_svstate_steps()
+ if pre:
self.svp64_reset_loop()
+ self.update_nia()
self.update_pc_next()
return
+ srcstep, dststep = self.new_srcstep, self.new_dststep
+ pred_dst_zero = self.pred_dst_zero
+ pred_src_zero = self.pred_src_zero
+ vl = self.svstate.vl.asint(msb0=True)
# VL=0 in SVP64 mode means "do nothing: skip instruction"
if self.is_svp64_mode and vl == 0:
self.namespace['NIA'])
return
+ # for when SVSHAPE is active, a very bad hack here (to be replaced)
+ # using pre-arranged schedule. all of this is awful but it is a
+ # start. next job will be to put the proper activation in place
+ yield self.dec2.remap_active.eq(1 if self.last_op_svshape else 0)
+ yield Settle()
+ if self.is_svp64_mode and self.last_op_svshape:
+ # get four SVSHAPEs. here we are hard-coding
+ # SVSHAPE0 to FRT, SVSHAPE1 to FRA, SVSHAPE2 to FRC and
+ # SVSHAPE3 to FRB, assuming "fmadd FRT, FRA, FRC, FRB."
+ SVSHAPE0 = self.spr['SVSHAPE0']
+ SVSHAPE1 = self.spr['SVSHAPE1']
+ SVSHAPE2 = self.spr['SVSHAPE2']
+ SVSHAPE3 = self.spr['SVSHAPE3']
+ for i in range(4):
+ sname = 'SVSHAPE%d' % i
+ shape = self.spr[sname]
+ print (sname, bin(shape.value))
+ print (" lims", shape.lims)
+ print (" mode", shape.mode)
+ print (" skip", shape.skip)
+
+ remaps = [(SVSHAPE0, SVSHAPE0.get_iterator()),
+ (SVSHAPE1, SVSHAPE1.get_iterator()),
+ (SVSHAPE2, SVSHAPE2.get_iterator()),
+ (SVSHAPE3, SVSHAPE3.get_iterator()),
+ ]
+ rremaps = []
+ for i, (shape, remap) in enumerate(remaps):
+ # zero is "disabled"
+ if shape.value == 0x0:
+ continue
+ # XXX hardcoded! pick dststep for out (i==0) else srcstep
+ if shape.mode == 0b00: # multiply mode
+ step = dststep if (i == 0) else srcstep
+ if shape.mode == 0b01: # FFT butterfly mode
+ step = srcstep # XXX HACK - for now only use srcstep
+ # this is terrible. O(N^2) looking for the match. but hey.
+ for idx, remap_idx in enumerate(remap):
+ if idx == step:
+ break
+ # multiply mode
+ if shape.mode == 0b00:
+ if i == 0:
+ yield self.dec2.o_step.eq(remap_idx) # RT
+ yield self.dec2.o2_step.eq(remap_idx) # EA
+ elif i == 1:
+ yield self.dec2.in1_step.eq(remap_idx) # RA
+ elif i == 2:
+ yield self.dec2.in3_step.eq(remap_idx) # RB
+ elif i == 3:
+ yield self.dec2.in2_step.eq(remap_idx) # RC
+ # FFT butterfly mode
+ if shape.mode == 0b01:
+ if i == 0:
+ yield self.dec2.o_step.eq(remap_idx) # RT
+ yield self.dec2.in2_step.eq(remap_idx) # RB
+ elif i == 1:
+ yield self.dec2.in1_step.eq(remap_idx) # RA
+ yield self.dec2.o2_step.eq(remap_idx) # EA (FRS)
+ elif i == 2:
+ yield self.dec2.in3_step.eq(remap_idx) # RC
+ elif i == 3:
+ pass # no SVSHAPE3
+ rremaps.append((shape.mode, i, idx, remap_idx)) # debug printing
+ for x in rremaps:
+ print ("shape remap", x)
+ # after that, settle down (combinatorial) to let Vector reg numbers
+ # work themselves out
+ yield Settle()
+ remap_active = yield self.dec2.remap_active
+ print ("remap active", remap_active)
+
# main input registers (RT, RA ...)
inputs = []
for name in input_names:
log('reading reg %s %s' % (name, str(regnum)), is_vec)
if name in fregs:
reg_val = self.fpr(regnum)
- else:
+ elif name is not None:
reg_val = self.gpr(regnum)
else:
log('zero input reg %s %s' % (name, str(regnum)), is_vec)
reg_val = 0
inputs.append(reg_val)
+ # arrrrgh, awful hack, to get _RT into namespace
+ if asmop == 'setvl':
+ regname = "_RT"
+ RT = yield self.dec2.dec.RT
+ self.namespace[regname] = SelectableInt(RT, 5)
+
+ # in SVP64 mode for LD/ST work out immediate
+ # XXX TODO: replace_ds for DS-Form rather than D-Form.
+ # use info.form to detect
+ replace_d = False # update / replace constant in pseudocode
+ if self.is_svp64_mode:
+ ldstmode = yield self.dec2.rm_dec.ldstmode
+ # bitreverse mode reads SVD (or SVDS - TODO)
+ # *BUT*... because this is "overloading" of LD operations,
+ # it gets *STORED* into D (or DS, TODO)
+ if ldstmode == SVP64LDSTmode.BITREVERSE.value:
+ imm = yield self.dec2.dec.fields.FormSVD.SVD[0:11]
+ imm = exts(imm, 11) # sign-extend to integer
+ print ("bitrev SVD", imm)
+ replace_d = True
+ else:
+ imm = yield self.dec2.dec.fields.FormD.D[0:16]
+ imm = exts(imm, 16) # sign-extend to integer
+ # get the right step. LD is from srcstep, ST is dststep
+ op = yield self.dec2.e.do.insn_type
+ offsmul = 0
+ if op == MicrOp.OP_LOAD.value:
+ offsmul = srcstep
+ log("D-field src", imm, offsmul)
+ elif op == MicrOp.OP_STORE.value:
+ offsmul = dststep
+ log("D-field dst", imm, offsmul)
+ # bit-reverse mode
+ if ldstmode == SVP64LDSTmode.BITREVERSE.value:
+ # manually look up RC, sigh
+ RC = yield self.dec2.dec.RC[0:5]
+ RC = self.gpr(RC)
+ log ("RC", RC.value, "imm", imm, "offs", bin(offsmul),
+ "rev", bin(bitrev(offsmul, vl)))
+ imm = SelectableInt((imm * bitrev(offsmul, vl)) << RC.value, 32)
+ # Unit-Strided LD/ST adds offset*width to immediate
+ elif ldstmode == SVP64LDSTmode.UNITSTRIDE.value:
+ ldst_len = yield self.dec2.e.do.data_len
+ imm = SelectableInt(imm + offsmul * ldst_len, 32)
+ replace_d = True
+ # Element-strided multiplies the immediate by element step
+ elif ldstmode == SVP64LDSTmode.ELSTRIDE.value:
+ imm = SelectableInt(imm * offsmul, 32)
+ replace_d = True
+ ldst_ra_vec = yield self.dec2.rm_dec.ldst_ra_vec
+ ldst_imz_in = yield self.dec2.rm_dec.ldst_imz_in
+ log("LDSTmode", ldstmode, SVP64LDSTmode.BITREVERSE.value,
+ offsmul, imm, ldst_ra_vec, ldst_imz_in)
+ # new replacement D
+ if replace_d:
+ self.namespace['D'] = imm
# "special" registers
for special in info.special_regs:
# clear trap (trap) NIA
self.trap_nia = None
- # execute actual instruction here
+ # execute actual instruction here (finally)
log("inputs", inputs)
results = info.func(self, *inputs)
log("results", results)
log("after func", self.namespace['CIA'], self.namespace['NIA'])
+ # check if op was a LD/ST so that debugging can check the
+ # address
+ if int_op in [MicrOp.OP_STORE.value,
+ ]:
+ self.last_st_addr = self.mem.last_st_addr
+ if int_op in [MicrOp.OP_LOAD.value,
+ ]:
+ self.last_ld_addr = self.mem.last_ld_addr
+ log ("op", int_op, MicrOp.OP_STORE.value, MicrOp.OP_LOAD.value,
+ self.last_st_addr, self.last_ld_addr)
+
# detect if CA/CA32 already in outputs (sra*, basically)
already_done = 0
if info.write_regs:
# check if it is the SVSTATE.src/dest step that needs incrementing
# this is our Sub-Program-Counter loop from 0 to VL-1
- if self.is_svp64_mode:
- # XXX twin predication TODO
- vl = self.svstate.vl.asint(msb0=True)
- mvl = self.svstate.maxvl.asint(msb0=True)
- srcstep = self.svstate.srcstep.asint(msb0=True)
- dststep = self.svstate.dststep.asint(msb0=True)
- sv_ptype = yield self.dec2.dec.op.SV_Ptype
- no_out_vec = not (yield self.dec2.no_out_vec)
- no_in_vec = not (yield self.dec2.no_in_vec)
- log (" svstate.vl", vl)
- log (" svstate.mvl", mvl)
- log (" svstate.srcstep", srcstep)
- log (" svstate.dststep", dststep)
- log (" no_out_vec", no_out_vec)
- log (" no_in_vec", no_in_vec)
- log (" sv_ptype", sv_ptype, sv_ptype == SVPtype.P2.value)
- # check if srcstep needs incrementing by one, stop PC advancing
- # svp64 loop can end early if the dest is scalar for single-pred
- # but for 2-pred both src/dest have to be checked.
- # XXX this might not be true! it may just be LD/ST
- if sv_ptype == SVPtype.P2.value:
- svp64_is_vector = (no_out_vec or no_in_vec)
+ pre = False
+ post = False
+ if self.allow_next_step_inc:
+ log("SVSTATE_NEXT: inc requested")
+ yield from self.svstate_pre_inc()
+ pre = yield from self.update_new_svstate_steps()
+ if pre:
+ # reset at end of loop including exit Vertical Mode
+ log ("SVSTATE_NEXT: end of loop, reset")
+ self.svp64_reset_loop()
+ self.msr[MSRb.SVF] = 0
+ self.update_nia()
+ if rc_en:
+ results = [SelectableInt(0, 64)]
+ self.handle_comparison(results) # CR0
else:
- svp64_is_vector = no_out_vec
- if svp64_is_vector and srcstep != vl-1 and dststep != vl-1:
- self.svstate.srcstep += SelectableInt(1, 7)
- self.svstate.dststep += SelectableInt(1, 7)
- self.pc.NIA.value = self.pc.CIA.value
- self.namespace['NIA'] = self.pc.NIA
+ log ("SVSTATE_NEXT: post-inc")
+ srcstep, dststep = self.new_srcstep, self.new_dststep
+ vl = self.svstate.vl.asint(msb0=True)
+ end_src = srcstep == vl-1
+ end_dst = dststep == vl-1
+ if not end_src:
+ self.svstate.srcstep += SelectableInt(1, 7)
+ if not end_dst:
+ self.svstate.dststep += SelectableInt(1, 7)
self.namespace['SVSTATE'] = self.svstate.spr
- log("end of sub-pc call", self.namespace['CIA'],
- self.namespace['NIA'])
- return # DO NOT allow PC to update whilst Sub-PC loop running
- # reset loop to zero
- self.svp64_reset_loop()
+ # set CR0 (if Rc=1) based on end
+ if rc_en:
+ srcstep = self.svstate.srcstep.asint(msb0=True)
+ dststep = self.svstate.srcstep.asint(msb0=True)
+ endtest = 0 if (end_src or end_dst) else 1
+ results = [SelectableInt(endtest, 64)]
+ self.handle_comparison(results) # CR0
+ if end_src or end_dst:
+ # reset at end of loop including exit Vertical Mode
+ log ("SVSTATE_NEXT: after increments, reset")
+ self.svp64_reset_loop()
+ self.msr[MSRb.SVF] = 0
+
+ elif self.is_svp64_mode:
+ yield from self.svstate_post_inc()
+ else:
+ # XXX only in non-SVP64 mode!
+ # record state of whether the current operation was an svshape,
+ # to be able to know if it should apply in the next instruction.
+ # also (if going to use this instruction) should disable ability
+ # to interrupt in between. sigh.
+ self.last_op_svshape = asmop == 'svremap'
self.update_pc_next()
+ def SVSTATE_NEXT(self):
+ """explicitly moves srcstep/dststep on to next element, for
+ "Vertical-First" mode. this function is called from
+ setvl pseudo-code, as a pseudo-op "svstep"
+ """
+ log("SVSTATE_NEXT")
+ self.allow_next_step_inc = True
+
+ def svstate_pre_inc(self):
+ """check if srcstep/dststep need to skip over masked-out predicate bits
+ """
+ # get SVSTATE VL (oh and print out some debug stuff)
+ vl = self.svstate.vl.asint(msb0=True)
+ srcstep = self.svstate.srcstep.asint(msb0=True)
+ dststep = self.svstate.dststep.asint(msb0=True)
+ sv_a_nz = yield self.dec2.sv_a_nz
+ fft_mode = yield self.dec2.use_svp64_fft
+ in1 = yield self.dec2.e.read_reg1.data
+ log ("SVP64: VL, srcstep, dststep, sv_a_nz, in1 fft",
+ vl, srcstep, dststep, sv_a_nz, in1, fft_mode)
+
+ # get predicate mask
+ srcmask = dstmask = 0xffff_ffff_ffff_ffff
+
+ pmode = yield self.dec2.rm_dec.predmode
+ reverse_gear = yield self.dec2.rm_dec.reverse_gear
+ sv_ptype = yield self.dec2.dec.op.SV_Ptype
+ srcpred = yield self.dec2.rm_dec.srcpred
+ dstpred = yield self.dec2.rm_dec.dstpred
+ pred_src_zero = yield self.dec2.rm_dec.pred_sz
+ pred_dst_zero = yield self.dec2.rm_dec.pred_dz
+ if pmode == SVP64PredMode.INT.value:
+ srcmask = dstmask = get_predint(self.gpr, dstpred)
+ if sv_ptype == SVPtype.P2.value:
+ srcmask = get_predint(self.gpr, srcpred)
+ elif pmode == SVP64PredMode.CR.value:
+ srcmask = dstmask = get_predcr(self.crl, dstpred, vl)
+ if sv_ptype == SVPtype.P2.value:
+ srcmask = get_predcr(self.crl, srcpred, vl)
+ log (" pmode", pmode)
+ log (" reverse", reverse_gear)
+ log (" ptype", sv_ptype)
+ log (" srcpred", bin(srcpred))
+ log (" dstpred", bin(dstpred))
+ log (" srcmask", bin(srcmask))
+ log (" dstmask", bin(dstmask))
+ log (" pred_sz", bin(pred_src_zero))
+ log (" pred_dz", bin(pred_dst_zero))
+
+ # okaaay, so here we simply advance srcstep (TODO dststep)
+ # until the predicate mask has a "1" bit... or we run out of VL
+ # let srcstep==VL be the indicator to move to next instruction
+ if not pred_src_zero:
+ while (((1<<srcstep) & srcmask) == 0) and (srcstep != vl):
+ log (" skip", bin(1<<srcstep))
+ srcstep += 1
+ # same for dststep
+ if not pred_dst_zero:
+ while (((1<<dststep) & dstmask) == 0) and (dststep != vl):
+ log (" skip", bin(1<<dststep))
+ dststep += 1
+
+ # now work out if the relevant mask bits require zeroing
+ if pred_dst_zero:
+ pred_dst_zero = ((1<<dststep) & dstmask) == 0
+ if pred_src_zero:
+ pred_src_zero = ((1<<srcstep) & srcmask) == 0
+
+ # store new srcstep / dststep
+ self.new_srcstep, self.new_dststep = srcstep, dststep
+ self.pred_dst_zero, self.pred_src_zero = pred_dst_zero, pred_src_zero
+ log (" new srcstep", srcstep)
+ log (" new dststep", dststep)
+
+ def update_new_svstate_steps(self):
+ srcstep, dststep = self.new_srcstep, self.new_dststep
+
+ # update SVSTATE with new srcstep
+ self.svstate.srcstep[0:7] = srcstep
+ self.svstate.dststep[0:7] = dststep
+ self.namespace['SVSTATE'] = self.svstate.spr
+ yield self.dec2.state.svstate.eq(self.svstate.spr.value)
+ yield Settle() # let decoder update
+ srcstep = self.svstate.srcstep.asint(msb0=True)
+ dststep = self.svstate.dststep.asint(msb0=True)
+ vl = self.svstate.vl.asint(msb0=True)
+ log (" srcstep", srcstep)
+ log (" dststep", dststep)
+
+ # check if end reached (we let srcstep overrun, above)
+ # nothing needs doing (TODO zeroing): just do next instruction
+ return srcstep == vl or dststep == vl
+
+ def svstate_post_inc(self, vf=0):
+ # check if SV "Vertical First" mode is enabled
+ log (" SV Vertical First", vf, self.msr[MSRb.SVF].value)
+ if not vf and self.msr[MSRb.SVF].value == 1:
+ self.update_nia()
+ return True
+
+ # check if it is the SVSTATE.src/dest step that needs incrementing
+ # this is our Sub-Program-Counter loop from 0 to VL-1
+ # XXX twin predication TODO
+ vl = self.svstate.vl.asint(msb0=True)
+ mvl = self.svstate.maxvl.asint(msb0=True)
+ srcstep = self.svstate.srcstep.asint(msb0=True)
+ dststep = self.svstate.dststep.asint(msb0=True)
+ rm_mode = yield self.dec2.rm_dec.mode
+ reverse_gear = yield self.dec2.rm_dec.reverse_gear
+ sv_ptype = yield self.dec2.dec.op.SV_Ptype
+ out_vec = not (yield self.dec2.no_out_vec)
+ in_vec = not (yield self.dec2.no_in_vec)
+ log (" svstate.vl", vl)
+ log (" svstate.mvl", mvl)
+ log (" svstate.srcstep", srcstep)
+ log (" svstate.dststep", dststep)
+ log (" mode", rm_mode)
+ log (" reverse", reverse_gear)
+ log (" out_vec", out_vec)
+ log (" in_vec", in_vec)
+ log (" sv_ptype", sv_ptype, sv_ptype == SVPtype.P2.value)
+ # check if srcstep needs incrementing by one, stop PC advancing
+ # svp64 loop can end early if the dest is scalar for single-pred
+ # but for 2-pred both src/dest have to be checked.
+ # XXX this might not be true! it may just be LD/ST
+ if sv_ptype == SVPtype.P2.value:
+ svp64_is_vector = (out_vec or in_vec)
+ else:
+ svp64_is_vector = out_vec
+ if svp64_is_vector and srcstep != vl-1 and dststep != vl-1:
+ self.svstate.srcstep += SelectableInt(1, 7)
+ self.svstate.dststep += SelectableInt(1, 7)
+ self.pc.NIA.value = self.pc.CIA.value
+ self.namespace['NIA'] = self.pc.NIA
+ self.namespace['SVSTATE'] = self.svstate.spr
+ log("end of sub-pc call", self.namespace['CIA'],
+ self.namespace['NIA'])
+ return False # DO NOT allow PC update whilst Sub-PC loop running
+
+ # reset loop to zero and update NIA
+ self.svp64_reset_loop()
+ self.update_nia()
+
+ return True
+
def update_pc_next(self):
# UPDATE program counter
self.pc.update(self.namespace, self.is_svp64_mode)
self.svstate.srcstep[0:7] = 0
self.svstate.dststep[0:7] = 0
log (" svstate.srcstep loop end (PC to update)")
+ self.namespace['SVSTATE'] = self.svstate.spr
+
+ def update_nia(self):
self.pc.update_nia(self.is_svp64_mode)
self.namespace['NIA'] = self.pc.NIA
- self.namespace['SVSTATE'] = self.svstate.spr
def inject():
"""Decorator factory.
projects / openpower-isa.git / blobdiff