self[i] = SelectableInt(regfile[i], 64)
def __call__(self, ridx):
+ if isinstance(ridx, SelectableInt):
+ ridx = ridx.value
return self[ridx]
def set_form(self, form):
self.form = form
+ def __setitem__(self, rnum, value):
+ # rnum = rnum.value # only SelectableInt allowed
+ log("GPR setitem", rnum, value)
+ if isinstance(rnum, SelectableInt):
+ rnum = rnum.value
+ dict.__setitem__(self, rnum, value)
+
def getz(self, rnum):
# rnum = rnum.value # only SelectableInt allowed
log("GPR getzero?", rnum)
return out, o_isvec
elif name == 'RT':
log ("get_pdecode_idx_out", out_sel, OutSel.RT.value,
- OutSel.RT_OR_ZERO.value, out, o_isvec)
+ OutSel.RT_OR_ZERO.value, out, o_isvec,
+ dec2.dec.RT)
if out_sel == OutSel.RT.value:
return out, o_isvec
elif name == 'FRA':
if name == 'FRS':
int_op = yield dec2.dec.op.internal_op
fft_en = yield dec2.use_svp64_fft
- if int_op == MicrOp.OP_FP_MADD.value and fft_en:
+ #if int_op == MicrOp.OP_FP_MADD.value and fft_en:
+ if fft_en:
log ("get_pdecode_idx_out2", out_sel, OutSel.FRS.value,
out, o_isvec)
return out, o_isvec
illegal = False
name = 'ffmadds'
+ # and ffadds not being supported by binutils (.long)
+ if asmop == 'ffadds':
+ illegal = False
+ name = 'ffadds'
+
if illegal:
print("illegal", name, asmop)
self.call_trap(0x700, PIb.ILLEG)
(name, asmop, self.pc.CIA.value))
return
+ # this is for setvl "Vertical" mode: if set true,
+ # srcstep/dststep is explicitly advanced
+ self.allow_next_step_inc = False
+
# nop has to be supported, we could let the actual op calculate
# but PowerDecoder has a pattern for nop
if name is 'nop':
dest_cr, src_cr, src_byname, dest_byname = False, False, {}, {}
log ("sv rm", sv_rm, dest_cr, src_cr, src_byname, dest_byname)
- # get SVSTATE VL (oh and print out some debug stuff)
- if self.is_svp64_mode:
- vl = self.svstate.vl.asint(msb0=True)
- srcstep = self.svstate.srcstep.asint(msb0=True)
- dststep = self.svstate.dststep.asint(msb0=True)
- sv_a_nz = yield self.dec2.sv_a_nz
- fft_mode = yield self.dec2.use_svp64_fft
- in1 = yield self.dec2.e.read_reg1.data
- log ("SVP64: VL, srcstep, dststep, sv_a_nz, in1 fft",
- vl, srcstep, dststep, sv_a_nz, in1, fft_mode)
-
- # get predicate mask
- srcmask = dstmask = 0xffff_ffff_ffff_ffff
+ # see if srcstep/dststep need skipping over masked-out predicate bits
if self.is_svp64_mode:
- pmode = yield self.dec2.rm_dec.predmode
- reverse_gear = yield self.dec2.rm_dec.reverse_gear
- sv_ptype = yield self.dec2.dec.op.SV_Ptype
- srcpred = yield self.dec2.rm_dec.srcpred
- dstpred = yield self.dec2.rm_dec.dstpred
- pred_src_zero = yield self.dec2.rm_dec.pred_sz
- pred_dst_zero = yield self.dec2.rm_dec.pred_dz
- if pmode == SVP64PredMode.INT.value:
- srcmask = dstmask = get_predint(self.gpr, dstpred)
- if sv_ptype == SVPtype.P2.value:
- srcmask = get_predint(self.gpr, srcpred)
- elif pmode == SVP64PredMode.CR.value:
- srcmask = dstmask = get_predcr(self.crl, dstpred, vl)
- if sv_ptype == SVPtype.P2.value:
- srcmask = get_predcr(self.crl, srcpred, vl)
- log (" pmode", pmode)
- log (" reverse", reverse_gear)
- log (" ptype", sv_ptype)
- log (" srcpred", bin(srcpred))
- log (" dstpred", bin(dstpred))
- log (" srcmask", bin(srcmask))
- log (" dstmask", bin(dstmask))
- log (" pred_sz", bin(pred_src_zero))
- log (" pred_dz", bin(pred_dst_zero))
-
- # okaaay, so here we simply advance srcstep (TODO dststep)
- # until the predicate mask has a "1" bit... or we run out of VL
- # let srcstep==VL be the indicator to move to next instruction
- if not pred_src_zero:
- while (((1<<srcstep) & srcmask) == 0) and (srcstep != vl):
- log (" skip", bin(1<<srcstep))
- srcstep += 1
- # same for dststep
- if not pred_dst_zero:
- while (((1<<dststep) & dstmask) == 0) and (dststep != vl):
- log (" skip", bin(1<<dststep))
- dststep += 1
-
- # now work out if the relevant mask bits require zeroing
- if pred_dst_zero:
- pred_dst_zero = ((1<<dststep) & dstmask) == 0
- if pred_src_zero:
- pred_src_zero = ((1<<srcstep) & srcmask) == 0
-
- # update SVSTATE with new srcstep
- self.svstate.srcstep[0:7] = srcstep
- self.svstate.dststep[0:7] = dststep
- self.namespace['SVSTATE'] = self.svstate.spr
- yield self.dec2.state.svstate.eq(self.svstate.spr.value)
- yield Settle() # let decoder update
- srcstep = self.svstate.srcstep.asint(msb0=True)
- dststep = self.svstate.dststep.asint(msb0=True)
- log (" srcstep", srcstep)
- log (" dststep", dststep)
-
- # check if end reached (we let srcstep overrun, above)
- # nothing needs doing (TODO zeroing): just do next instruction
- if srcstep == vl or dststep == vl:
+ yield from self.svstate_pre_inc()
+ pre = yield from self.update_new_svstate_steps()
+ if pre:
self.svp64_reset_loop()
+ self.update_nia()
self.update_pc_next()
return
+ srcstep, dststep = self.new_srcstep, self.new_dststep
+ pred_dst_zero = self.pred_dst_zero
+ pred_src_zero = self.pred_src_zero
+ vl = self.svstate.vl.asint(msb0=True)
# VL=0 in SVP64 mode means "do nothing: skip instruction"
if self.is_svp64_mode and vl == 0:
# using pre-arranged schedule. all of this is awful but it is a
# start. next job will be to put the proper activation in place
yield self.dec2.remap_active.eq(1 if self.last_op_svshape else 0)
+ yield Settle()
if self.is_svp64_mode and self.last_op_svshape:
# get four SVSHAPEs. here we are hard-coding
# SVSHAPE0 to FRT, SVSHAPE1 to FRA, SVSHAPE2 to FRC and
if shape.mode == 0b01:
if i == 0:
yield self.dec2.o_step.eq(remap_idx) # RT
- yield self.dec2.in1_step.eq(remap_idx) # RA
- elif i == 1:
yield self.dec2.in2_step.eq(remap_idx) # RB
+ elif i == 1:
+ yield self.dec2.in1_step.eq(remap_idx) # RA
yield self.dec2.o2_step.eq(remap_idx) # EA (FRS)
elif i == 2:
yield self.dec2.in3_step.eq(remap_idx) # RC
log('reading reg %s %s' % (name, str(regnum)), is_vec)
if name in fregs:
reg_val = self.fpr(regnum)
- else:
+ elif name is not None:
reg_val = self.gpr(regnum)
else:
log('zero input reg %s %s' % (name, str(regnum)), is_vec)
reg_val = 0
inputs.append(reg_val)
+ # arrrrgh, awful hack, to get _RT into namespace
+ if asmop == 'setvl':
+ regname = "_RT"
+ RT = yield self.dec2.dec.RT
+ self.namespace[regname] = SelectableInt(RT, 5)
# in SVP64 mode for LD/ST work out immediate
# XXX TODO: replace_ds for DS-Form rather than D-Form.
# check if it is the SVSTATE.src/dest step that needs incrementing
# this is our Sub-Program-Counter loop from 0 to VL-1
- if self.is_svp64_mode:
- # XXX twin predication TODO
- vl = self.svstate.vl.asint(msb0=True)
- mvl = self.svstate.maxvl.asint(msb0=True)
- srcstep = self.svstate.srcstep.asint(msb0=True)
- dststep = self.svstate.dststep.asint(msb0=True)
- rm_mode = yield self.dec2.rm_dec.mode
- reverse_gear = yield self.dec2.rm_dec.reverse_gear
- sv_ptype = yield self.dec2.dec.op.SV_Ptype
- out_vec = not (yield self.dec2.no_out_vec)
- in_vec = not (yield self.dec2.no_in_vec)
- log (" svstate.vl", vl)
- log (" svstate.mvl", mvl)
- log (" svstate.srcstep", srcstep)
- log (" svstate.dststep", dststep)
- log (" mode", rm_mode)
- log (" reverse", reverse_gear)
- log (" out_vec", out_vec)
- log (" in_vec", in_vec)
- log (" sv_ptype", sv_ptype, sv_ptype == SVPtype.P2.value)
- # check if srcstep needs incrementing by one, stop PC advancing
- # svp64 loop can end early if the dest is scalar for single-pred
- # but for 2-pred both src/dest have to be checked.
- # XXX this might not be true! it may just be LD/ST
- if sv_ptype == SVPtype.P2.value:
- svp64_is_vector = (out_vec or in_vec)
+ pre = False
+ post = False
+ if self.allow_next_step_inc:
+ log("SVSTATE_NEXT: inc requested")
+ yield from self.svstate_pre_inc()
+ pre = yield from self.update_new_svstate_steps()
+ if pre:
+ # reset at end of loop including exit Vertical Mode
+ log ("SVSTATE_NEXT: end of loop, reset")
+ self.svp64_reset_loop()
+ self.msr[MSRb.SVF] = 0
+ self.update_nia()
+ if rc_en:
+ results = [SelectableInt(0, 64)]
+ self.handle_comparison(results) # CR0
else:
- svp64_is_vector = out_vec
- if svp64_is_vector and srcstep != vl-1 and dststep != vl-1:
- self.svstate.srcstep += SelectableInt(1, 7)
- self.svstate.dststep += SelectableInt(1, 7)
- self.pc.NIA.value = self.pc.CIA.value
- self.namespace['NIA'] = self.pc.NIA
+ log ("SVSTATE_NEXT: post-inc")
+ srcstep, dststep = self.new_srcstep, self.new_dststep
+ vl = self.svstate.vl.asint(msb0=True)
+ end_src = srcstep == vl-1
+ end_dst = dststep == vl-1
+ if not end_src:
+ self.svstate.srcstep += SelectableInt(1, 7)
+ if not end_dst:
+ self.svstate.dststep += SelectableInt(1, 7)
self.namespace['SVSTATE'] = self.svstate.spr
- log("end of sub-pc call", self.namespace['CIA'],
- self.namespace['NIA'])
- return # DO NOT allow PC to update whilst Sub-PC loop running
- # reset loop to zero
- self.svp64_reset_loop()
-
- # XXX only in non-SVP64 mode!
- # record state of whether the current operation was an svshape,
- # to be able to know if it should apply in the next instruction.
- # also (if going to use this instruction) should disable ability
- # to interrupt in between. sigh.
- self.last_op_svshape = asmop == 'svremap'
+ # set CR0 (if Rc=1) based on end
+ if rc_en:
+ srcstep = self.svstate.srcstep.asint(msb0=True)
+ dststep = self.svstate.srcstep.asint(msb0=True)
+ endtest = 0 if (end_src or end_dst) else 1
+ results = [SelectableInt(endtest, 64)]
+ self.handle_comparison(results) # CR0
+ if end_src or end_dst:
+ # reset at end of loop including exit Vertical Mode
+ log ("SVSTATE_NEXT: after increments, reset")
+ self.svp64_reset_loop()
+ self.msr[MSRb.SVF] = 0
+
+ elif self.is_svp64_mode:
+ yield from self.svstate_post_inc()
+ else:
+ # XXX only in non-SVP64 mode!
+ # record state of whether the current operation was an svshape,
+ # to be able to know if it should apply in the next instruction.
+ # also (if going to use this instruction) should disable ability
+ # to interrupt in between. sigh.
+ self.last_op_svshape = asmop == 'svremap'
self.update_pc_next()
+ def SVSTATE_NEXT(self):
+ """explicitly moves srcstep/dststep on to next element, for
+ "Vertical-First" mode. this function is called from
+ setvl pseudo-code, as a pseudo-op "svstep"
+ """
+ log("SVSTATE_NEXT")
+ self.allow_next_step_inc = True
+
+ def svstate_pre_inc(self):
+ """check if srcstep/dststep need to skip over masked-out predicate bits
+ """
+ # get SVSTATE VL (oh and print out some debug stuff)
+ vl = self.svstate.vl.asint(msb0=True)
+ srcstep = self.svstate.srcstep.asint(msb0=True)
+ dststep = self.svstate.dststep.asint(msb0=True)
+ sv_a_nz = yield self.dec2.sv_a_nz
+ fft_mode = yield self.dec2.use_svp64_fft
+ in1 = yield self.dec2.e.read_reg1.data
+ log ("SVP64: VL, srcstep, dststep, sv_a_nz, in1 fft",
+ vl, srcstep, dststep, sv_a_nz, in1, fft_mode)
+
+ # get predicate mask
+ srcmask = dstmask = 0xffff_ffff_ffff_ffff
+
+ pmode = yield self.dec2.rm_dec.predmode
+ reverse_gear = yield self.dec2.rm_dec.reverse_gear
+ sv_ptype = yield self.dec2.dec.op.SV_Ptype
+ srcpred = yield self.dec2.rm_dec.srcpred
+ dstpred = yield self.dec2.rm_dec.dstpred
+ pred_src_zero = yield self.dec2.rm_dec.pred_sz
+ pred_dst_zero = yield self.dec2.rm_dec.pred_dz
+ if pmode == SVP64PredMode.INT.value:
+ srcmask = dstmask = get_predint(self.gpr, dstpred)
+ if sv_ptype == SVPtype.P2.value:
+ srcmask = get_predint(self.gpr, srcpred)
+ elif pmode == SVP64PredMode.CR.value:
+ srcmask = dstmask = get_predcr(self.crl, dstpred, vl)
+ if sv_ptype == SVPtype.P2.value:
+ srcmask = get_predcr(self.crl, srcpred, vl)
+ log (" pmode", pmode)
+ log (" reverse", reverse_gear)
+ log (" ptype", sv_ptype)
+ log (" srcpred", bin(srcpred))
+ log (" dstpred", bin(dstpred))
+ log (" srcmask", bin(srcmask))
+ log (" dstmask", bin(dstmask))
+ log (" pred_sz", bin(pred_src_zero))
+ log (" pred_dz", bin(pred_dst_zero))
+
+ # okaaay, so here we simply advance srcstep (TODO dststep)
+ # until the predicate mask has a "1" bit... or we run out of VL
+ # let srcstep==VL be the indicator to move to next instruction
+ if not pred_src_zero:
+ while (((1<<srcstep) & srcmask) == 0) and (srcstep != vl):
+ log (" skip", bin(1<<srcstep))
+ srcstep += 1
+ # same for dststep
+ if not pred_dst_zero:
+ while (((1<<dststep) & dstmask) == 0) and (dststep != vl):
+ log (" skip", bin(1<<dststep))
+ dststep += 1
+
+ # now work out if the relevant mask bits require zeroing
+ if pred_dst_zero:
+ pred_dst_zero = ((1<<dststep) & dstmask) == 0
+ if pred_src_zero:
+ pred_src_zero = ((1<<srcstep) & srcmask) == 0
+
+ # store new srcstep / dststep
+ self.new_srcstep, self.new_dststep = srcstep, dststep
+ self.pred_dst_zero, self.pred_src_zero = pred_dst_zero, pred_src_zero
+ log (" new srcstep", srcstep)
+ log (" new dststep", dststep)
+
+ def update_new_svstate_steps(self):
+ srcstep, dststep = self.new_srcstep, self.new_dststep
+
+ # update SVSTATE with new srcstep
+ self.svstate.srcstep[0:7] = srcstep
+ self.svstate.dststep[0:7] = dststep
+ self.namespace['SVSTATE'] = self.svstate.spr
+ yield self.dec2.state.svstate.eq(self.svstate.spr.value)
+ yield Settle() # let decoder update
+ srcstep = self.svstate.srcstep.asint(msb0=True)
+ dststep = self.svstate.dststep.asint(msb0=True)
+ vl = self.svstate.vl.asint(msb0=True)
+ log (" srcstep", srcstep)
+ log (" dststep", dststep)
+
+ # check if end reached (we let srcstep overrun, above)
+ # nothing needs doing (TODO zeroing): just do next instruction
+ return srcstep == vl or dststep == vl
+
+ def svstate_post_inc(self, vf=0):
+ # check if SV "Vertical First" mode is enabled
+ log (" SV Vertical First", vf, self.msr[MSRb.SVF].value)
+ if not vf and self.msr[MSRb.SVF].value == 1:
+ self.update_nia()
+ return True
+
+ # check if it is the SVSTATE.src/dest step that needs incrementing
+ # this is our Sub-Program-Counter loop from 0 to VL-1
+ # XXX twin predication TODO
+ vl = self.svstate.vl.asint(msb0=True)
+ mvl = self.svstate.maxvl.asint(msb0=True)
+ srcstep = self.svstate.srcstep.asint(msb0=True)
+ dststep = self.svstate.dststep.asint(msb0=True)
+ rm_mode = yield self.dec2.rm_dec.mode
+ reverse_gear = yield self.dec2.rm_dec.reverse_gear
+ sv_ptype = yield self.dec2.dec.op.SV_Ptype
+ out_vec = not (yield self.dec2.no_out_vec)
+ in_vec = not (yield self.dec2.no_in_vec)
+ log (" svstate.vl", vl)
+ log (" svstate.mvl", mvl)
+ log (" svstate.srcstep", srcstep)
+ log (" svstate.dststep", dststep)
+ log (" mode", rm_mode)
+ log (" reverse", reverse_gear)
+ log (" out_vec", out_vec)
+ log (" in_vec", in_vec)
+ log (" sv_ptype", sv_ptype, sv_ptype == SVPtype.P2.value)
+ # check if srcstep needs incrementing by one, stop PC advancing
+ # svp64 loop can end early if the dest is scalar for single-pred
+ # but for 2-pred both src/dest have to be checked.
+ # XXX this might not be true! it may just be LD/ST
+ if sv_ptype == SVPtype.P2.value:
+ svp64_is_vector = (out_vec or in_vec)
+ else:
+ svp64_is_vector = out_vec
+ if svp64_is_vector and srcstep != vl-1 and dststep != vl-1:
+ self.svstate.srcstep += SelectableInt(1, 7)
+ self.svstate.dststep += SelectableInt(1, 7)
+ self.pc.NIA.value = self.pc.CIA.value
+ self.namespace['NIA'] = self.pc.NIA
+ self.namespace['SVSTATE'] = self.svstate.spr
+ log("end of sub-pc call", self.namespace['CIA'],
+ self.namespace['NIA'])
+ return False # DO NOT allow PC update whilst Sub-PC loop running
+
+ # reset loop to zero and update NIA
+ self.svp64_reset_loop()
+ self.update_nia()
+
+ return True
+
def update_pc_next(self):
# UPDATE program counter
self.pc.update(self.namespace, self.is_svp64_mode)
self.svstate.srcstep[0:7] = 0
self.svstate.dststep[0:7] = 0
log (" svstate.srcstep loop end (PC to update)")
- self.pc.update_nia(self.is_svp64_mode)
- self.namespace['NIA'] = self.pc.NIA
self.namespace['SVSTATE'] = self.svstate.spr
+ def update_nia(self):
+ self.pc.update_nia(self.is_svp64_mode)
+ self.namespace['NIA'] = self.pc.NIA
def inject():
"""Decorator factory.
projects / openpower-isa.git / blobdiff