add (untested) TestRunner based on soc test_runner.py

[openpower-isa.git] / src / openpower / decoder / isa / caller.py

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 3fabdec46b5ca836163f813af03e984f73e38938..413494ca0a3d952c1c10fd0420eda7116694c141 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -28,7 +28,7 @@ from openpower.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
 
 from openpower.decoder.power_enums import SVPtype
 
-from openpower.decoder.helpers import (exts, gtu, ltu, undefined, bitrev)
+from openpower.decoder.helpers import (exts, gtu, ltu, undefined)
 from openpower.consts import PIb, MSRb  # big-endian (PowerISA versions)
 from openpower.consts import SVP64CROffs
 from openpower.decoder.power_svp64 import SVP64RM, decode_extra
@@ -1027,8 +1027,11 @@ class ISACaller:
         return asmop
 
     def get_remap_indices(self):
+        """WARNING, this function stores remap_idxs and remap_loopends
+        in the class for later use.  this to avoid problems with yield
+        """
         # go through all iterators in lock-step, advance to next remap_idx
-        srcstep, dststep = self.new_srcstep, self.new_dststep
+        srcstep, dststep = self.get_src_dststeps()
         # get four SVSHAPEs. here we are hard-coding
         SVSHAPE0 = self.spr['SVSHAPE0']
         SVSHAPE1 = self.spr['SVSHAPE1']
@@ -1203,7 +1206,7 @@ class ISACaller:
                 self.update_nia()
                 self.update_pc_next()
                 return
-            srcstep, dststep = self.new_srcstep, self.new_dststep
+            srcstep, dststep = self.get_src_dststeps()
             pred_dst_zero = self.pred_dst_zero
             pred_src_zero = self.pred_src_zero
             vl = self.svstate.vl
@@ -1313,13 +1316,13 @@ class ISACaller:
         replace_d = False # update / replace constant in pseudocode
         if self.is_svp64_mode:
             ldstmode = yield self.dec2.rm_dec.ldstmode
-            # bitreverse mode reads SVD (or SVDS - TODO)
+            # shift mode reads SVD (or SVDS - TODO)
             # *BUT*... because this is "overloading" of LD operations,
             # it gets *STORED* into D (or DS, TODO)
-            if ldstmode == SVP64LDSTmode.BITREVERSE.value:
+            if ldstmode == SVP64LDSTmode.SHIFT.value:
                 imm = yield self.dec2.dec.fields.FormSVD.SVD[0:11]
                 imm = exts(imm, 11) # sign-extend to integer
-                log ("bitrev SVD", imm)
+                log ("shift SVD", imm)
                 replace_d = True
             else:
                 if info.form == 'DS':
@@ -1332,19 +1335,26 @@ class ISACaller:
             op = yield self.dec2.e.do.insn_type
             offsmul = 0
             if op == MicrOp.OP_LOAD.value:
-                offsmul = srcstep
-                log("D-field src", imm, offsmul)
+                if remap_active:
+                    offsmul = yield self.dec2.in1_step
+                    log("D-field REMAP src", imm, offsmul)
+                else:
+                    offsmul = srcstep
+                    log("D-field src", imm, offsmul)
             elif op == MicrOp.OP_STORE.value:
+                # XXX NOTE! no bit-reversed STORE! this should not ever be used
                 offsmul = dststep
                 log("D-field dst", imm, offsmul)
-            # bit-reverse mode
-            if ldstmode == SVP64LDSTmode.BITREVERSE.value:
+            # bit-reverse mode, rev already done through get_src_dst_steps()
+            if ldstmode == SVP64LDSTmode.SHIFT.value:
                 # manually look up RC, sigh
                 RC = yield self.dec2.dec.RC[0:5]
                 RC = self.gpr(RC)
-                log ("RC", RC.value, "imm", imm, "offs", bin(offsmul),
-                     "rev", bin(bitrev(offsmul, vl)))
-                imm = SelectableInt((imm * bitrev(offsmul, vl)) << RC.value, 32)
+                log ("LD-SHIFT:", "VL", vl,
+                      "RC", RC.value, "imm", imm,
+                     "offs", bin(offsmul),
+                     )
+                imm = SelectableInt((imm * offsmul) << RC.value, 32)
             # Unit-Strided LD/ST adds offset*width to immediate
             elif ldstmode == SVP64LDSTmode.UNITSTRIDE.value:
                 ldst_len = yield self.dec2.e.do.data_len
@@ -1520,6 +1530,8 @@ class ISACaller:
                     yield from self.svstate_post_inc()
                 else:
                     log ("SVSTATE_NEXT: post-inc")
+                # use actual src/dst-step here to check end, do NOT
+                # use bit-reversed version
                 srcstep, dststep = self.new_srcstep, self.new_dststep
                 remaps = self.get_remap_indices()
                 remap_idxs = self.remap_idxs
@@ -1570,6 +1582,10 @@ class ISACaller:
         """explicitly moves srcstep/dststep on to next element, for
         "Vertical-First" mode.  this function is called from
         setvl pseudo-code, as a pseudo-op "svstep"
+
+        WARNING: this function uses information that was created EARLIER
+        due to it being in the middle of a yield, but this function is
+        *NOT* called from yield (it's called from compiled pseudocode).
         """
         self.allow_next_step_inc = submode.value + 1
         log("SVSTATE_NEXT mode", mode, submode, self.allow_next_step_inc)
@@ -1646,7 +1662,13 @@ class ISACaller:
         log ("    new srcstep", srcstep)
         log ("    new dststep", dststep)
 
+    def get_src_dststeps(self):
+        """gets srcstep and dststep 
+        """
+        return self.new_srcstep, self.new_dststep
+
     def update_new_svstate_steps(self):
+        # note, do not get the bit-reversed srcstep here!
         srcstep, dststep = self.new_srcstep, self.new_dststep
 
         # update SVSTATE with new srcstep