SVP64LDSTmode, SVP64PredCR,
SVP64PredInt, SVP64PredMode,
SVP64RMMode, SVPType, XER_bits,
- insns, spr_byname, spr_dict)
+ insns, spr_byname, spr_dict,
+ BFP_FLAG_NAMES)
from openpower.decoder.power_insn import SVP64Instruction
from openpower.decoder.power_svp64 import SVP64RM, decode_extra
from openpower.decoder.selectable_int import (FieldSelectableInt,
- SelectableInt, selectconcat)
+ SelectableInt, selectconcat,
+ EFFECTIVELY_UNLIMITED)
+from openpower.fpscr import FPSCRState
+from openpower.xer import XERState
from openpower.util import LogKind, log
+LDST_UPDATE_INSNS = ['ldu', 'lwzu', 'lbzu', 'lhzu', 'lhau', 'lfsu', 'lfdu',
+ ]
+
instruction_info = namedtuple('instruction_info',
'func read_regs uninit_regs write_regs ' +
'special_regs op_fields form asmregs')
"CTR": 0,
"TAR": 0,
"MSR": 0,
+ "FPSCR": 0,
"SVSTATE": 0,
"SVSHAPE0": 0,
"SVSHAPE1": 0,
info = spr_dict[key]
else:
info = spr_byname[key]
- dict.__setitem__(self, key, SelectableInt(0, info.length))
+ self[key] = SelectableInt(0, info.length)
res = dict.__getitem__(self, key)
log("spr returning", key, res)
return res
self.__setitem__('SRR0', value)
if key == 'HSRR1': # HACK!
self.__setitem__('SRR1', value)
+ if key == 1:
+ value = XERState(value)
log("setting spr", key, value)
dict.__setitem__(self, key, value)
elif name == 'FRA':
if in1_sel == In1Sel.FRA.value:
return 1
+ if in3_sel == In3Sel.FRA.value:
+ return 3
elif name == 'FRB':
if in2_sel == In2Sel.FRB.value:
return 2
return 1
if in3_sel == In3Sel.FRS.value:
return 3
+ elif name == 'FRT':
+ if in1_sel == In1Sel.FRT.value:
+ return 1
+ elif name == 'RT':
+ if in1_sel == In1Sel.RT.value:
+ return 1
return None
if name == 'CR1': # these are not actually calculated correctly
if out_sel == CROutSel.CR1.value:
return out, o_isvec
+ # check RC1 set? if so return implicit vector, this is a REAL bad hack
+ RC1 = yield dec2.rm_dec.RC1
+ if RC1:
+ log("get_cr_out RC1 mode")
+ if name == 'CR0':
+ return 0, True # XXX TODO: offset CR0 from SVSTATE SPR
+ if name == 'CR1':
+ return 1, True # XXX TODO: offset CR1 from SVSTATE SPR
+ # nope - not found.
log("get_cr_out not found", name)
return None, False
elif name == 'FRA':
if out_sel == OutSel.FRA.value:
return True
+ elif name == 'FRS':
+ if out_sel == OutSel.FRS.value:
+ return True
elif name == 'FRT':
if out_sel == OutSel.FRT.value:
return True
initial_pc=0,
bigendian=False,
mmu=False,
- icachemmu=False):
+ icachemmu=False,
+ initial_fpscr=0):
self.bigendian = bigendian
self.halted = False
# FPR (same as GPR except for FP nums)
# 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
# note that mffs, mcrfs, mtfsf "manage" this FPSCR
+ self.fpscr = FPSCRState(initial_fpscr)
+
# 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
# note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
# -- Done
self.cr_backup = 0 # sigh, dreadful hack: for fail-first (VLi)
# "undefined", just set to variable-bit-width int (use exts "max")
- # self.undefined = SelectableInt(0, 256) # TODO, not hard-code 256!
+ # self.undefined = SelectableInt(0, EFFECTIVELY_UNLIMITED)
self.namespace = {}
self.namespace.update(self.spr)
'SVSHAPE3': self.spr['SVSHAPE3'],
'CR': self.cr,
'MSR': self.msr,
+ 'FPSCR': self.fpscr,
'undefined': undefined,
'mode_is_64bit': True,
'SO': XER_bits['SO'],
'XLEN': 64 # elwidth overrides
})
+ for name in BFP_FLAG_NAMES:
+ setattr(self, name, 0)
+
# update pc to requested start point
self.set_pc(initial_pc)
self.decoder = decoder2.dec
self.dec2 = decoder2
- super().__init__(XLEN=self.namespace["XLEN"])
+ super().__init__(XLEN=self.namespace["XLEN"], FPSCR=self.fpscr)
@property
def XLEN(self):
return self.namespace["XLEN"]
+ @property
+ def FPSCR(self):
+ return self.fpscr
+
def call_trap(self, trap_addr, trap_bit):
"""calls TRAP and sets up NIA to the new execution location.
next instruction will begin at trap_addr.
self.namespace['XER'] = self.spr['XER']
self.namespace['CA'] = self.spr['XER'][XER_bits['CA']].value
self.namespace['CA32'] = self.spr['XER'][XER_bits['CA32']].value
+ self.namespace['OV'] = self.spr['XER'][XER_bits['OV']].value
+ self.namespace['OV32'] = self.spr['XER'][XER_bits['OV32']].value
self.namespace['XLEN'] = xlen
# add some SVSTATE convenience variables
self.namespace['sz'] = SelectableInt(sz, 1)
self.namespace['SNZ'] = SelectableInt(bc_snz, 1)
- def handle_carry_(self, inputs, output, ca, ca32):
+ def get_kludged_op_add_ca_ov(self, inputs, inp_ca_ov):
+ """ this was not at all necessary to do. this function massively
+ duplicates - in a laborious and complex fashion - the contents of
+ the CSV files that were extracted two years ago from microwatt's
+ source code. A-inversion is the "inv A" column, output inversion
+ is the "inv out" column, carry-in equal to 0 or 1 or CA is the
+ "cry in" column
+
+ all of that information is available in
+ self.instrs[ins_name].op_fields
+ where info is usually assigned to self.instrs[ins_name]
+
+ https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isatables/minor_31.csv;hb=HEAD
+
+ the immediate constants are *also* decoded correctly and placed
+ usually by DecodeIn2Imm into operand2, as part of power_decoder2.py
+ """
+ def ca(a, b, ca_in, width):
+ mask = (1 << width) - 1
+ y = (a & mask) + (b & mask) + ca_in
+ return y >> width
+
+ asmcode = yield self.dec2.dec.op.asmcode
+ insn = insns.get(asmcode)
+ SI = yield self.dec2.dec.SI
+ SI &= 0xFFFF
+ CA, OV = inp_ca_ov
+ inputs = [i.value for i in inputs]
+ if SI & 0x8000:
+ SI -= 0x10000
+ if insn in ("add", "addo", "addc", "addco"):
+ a = inputs[0]
+ b = inputs[1]
+ ca_in = 0
+ elif insn == "addic" or insn == "addic.":
+ a = inputs[0]
+ b = SI
+ ca_in = 0
+ elif insn in ("subf", "subfo", "subfc", "subfco"):
+ a = ~inputs[0]
+ b = inputs[1]
+ ca_in = 1
+ elif insn == "subfic":
+ a = ~inputs[0]
+ b = SI
+ ca_in = 1
+ elif insn == "adde" or insn == "addeo":
+ a = inputs[0]
+ b = inputs[1]
+ ca_in = CA
+ elif insn == "subfe" or insn == "subfeo":
+ a = ~inputs[0]
+ b = inputs[1]
+ ca_in = CA
+ elif insn == "addme" or insn == "addmeo":
+ a = inputs[0]
+ b = ~0
+ ca_in = CA
+ elif insn == "addze" or insn == "addzeo":
+ a = inputs[0]
+ b = 0
+ ca_in = CA
+ elif insn == "subfme" or insn == "subfmeo":
+ a = ~inputs[0]
+ b = ~0
+ ca_in = CA
+ elif insn == "subfze" or insn == "subfzeo":
+ a = ~inputs[0]
+ b = 0
+ ca_in = CA
+ elif insn == "addex":
+ # CA[32] aren't actually written, just generate so we have
+ # something to return
+ ca64 = ov64 = ca(inputs[0], inputs[1], OV, 64)
+ ca32 = ov32 = ca(inputs[0], inputs[1], OV, 32)
+ return ca64, ca32, ov64, ov32
+ elif insn == "neg" or insn == "nego":
+ a = ~inputs[0]
+ b = 0
+ ca_in = 1
+ else:
+ raise NotImplementedError(
+ "op_add kludge unimplemented instruction: ", asmcode, insn)
+
+ ca64 = ca(a, b, ca_in, 64)
+ ca32 = ca(a, b, ca_in, 32)
+ ov64 = ca64 != ca(a, b, ca_in, 63)
+ ov32 = ca32 != ca(a, b, ca_in, 31)
+ return ca64, ca32, ov64, ov32
+
+ def handle_carry_(self, inputs, output, ca, ca32, inp_ca_ov):
+ op = yield self.dec2.e.do.insn_type
+ if op == MicrOp.OP_ADD.value and ca is None and ca32 is None:
+ retval = yield from self.get_kludged_op_add_ca_ov(
+ inputs, inp_ca_ov)
+ ca, ca32, ov, ov32 = retval
+ asmcode = yield self.dec2.dec.op.asmcode
+ if insns.get(asmcode) == 'addex':
+ # TODO: if 32-bit mode, set ov to ov32
+ self.spr['XER'][XER_bits['OV']] = ov
+ self.spr['XER'][XER_bits['OV32']] = ov32
+ else:
+ # TODO: if 32-bit mode, set ca to ca32
+ self.spr['XER'][XER_bits['CA']] = ca
+ self.spr['XER'][XER_bits['CA32']] = ca32
+ return
inv_a = yield self.dec2.e.do.invert_in
if inv_a:
inputs[0] = ~inputs[0]
if ca32 is None: # already written
self.spr['XER'][XER_bits['CA32']] = cy32
- def handle_overflow(self, inputs, output, div_overflow):
+ def handle_overflow(self, inputs, output, div_overflow, inp_ca_ov):
+ op = yield self.dec2.e.do.insn_type
+ if op == MicrOp.OP_ADD.value:
+ retval = yield from self.get_kludged_op_add_ca_ov(
+ inputs, inp_ca_ov)
+ ca, ca32, ov, ov32 = retval
+ # TODO: if 32-bit mode, set ov to ov32
+ self.spr['XER'][XER_bits['OV']] = ov
+ self.spr['XER'][XER_bits['OV32']] = ov32
+ self.spr['XER'][XER_bits['SO']] |= ov
+ return
if hasattr(self.dec2.e.do, "invert_in"):
inv_a = yield self.dec2.e.do.invert_in
if inv_a:
def execute_one(self):
"""execute one instruction
"""
+ self.insnlog = [] # log the instruction
# get the disassembly code for this instruction
if not self.disassembly:
code = yield from self.get_assembly_name()
offs, dbg = 4, "svp64 "
code = self.disassembly[self._pc+offs]
log(" %s sim-execute" % dbg, hex(self._pc), code)
+ self.insnlog.append(code)
opname = code.split(' ')[0]
try:
yield from self.call(opname) # execute the instruction
# not supported yet:
raise e # ... re-raise
+ # append the log file
+ with open("/tmp/insnlog.txt", "a+") as f:
+ f.write(" ".join(self.insnlog)+"\n")
+
log("gprs after code", code)
self.gpr.dump()
crs = []
# list of instructions not being supported by binutils (.long)
dotstrp = asmop[:-1] if asmop[-1] == '.' else asmop
if dotstrp in [*FPTRANS_INSNS,
+ *LDST_UPDATE_INSNS,
'ffmadds', 'fdmadds', 'ffadds',
- 'mins', 'maxs', 'minu', 'maxu',
+ 'minmax',
'setvl', 'svindex', 'svremap', 'svstep',
'svshape', 'svshape2',
'grev', 'ternlogi', 'bmask', 'cprop',
'absdu', 'absds', 'absdacs', 'absdacu', 'avgadd',
'fmvis', 'fishmv', 'pcdec', "maddedu", "divmod2du",
"dsld", "dsrd", "maddedus",
- "shadd", "shadduw",
+ "shadd", "shaddw", "shadduw",
+ "fcvttg", "fcvttgo", "fcvttgs", "fcvttgso",
+ "fmvtg", "fmvtgs",
+ "fcvtfg", "fcvtfgs",
+ "fmvfg", "fmvfgs",
+ "maddsubrs", "maddrs"
]:
illegal = False
ins_name = dotstrp
end_loop = no_in_vec or srcstep == vl-1 or dststep == vl-1
self.namespace['end_loop'] = SelectableInt(end_loop, 1)
+ inp_ca_ov = (self.spr['XER'][XER_bits['CA']].value,
+ self.spr['XER'][XER_bits['OV']].value)
+
# execute actual instruction here (finally)
log("inputs", inputs)
results = info.func(self, *inputs)
log("carry already done?", ca, ca32, output_names)
carry_en = yield self.dec2.e.do.output_carry
if carry_en:
- yield from self.handle_carry_(inputs, results[0], ca, ca32)
+ yield from self.handle_carry_(
+ inputs, results[0], ca, ca32, inp_ca_ov=inp_ca_ov)
# get outout named "overflow" and "CR0"
overflow = outs.get('overflow')
ov_ok = yield self.dec2.e.do.oe.ok
log("internal overflow", ins_name, overflow, "en?", ov_en, ov_ok)
if ov_en & ov_ok:
- yield from self.handle_overflow(inputs, results[0], overflow)
+ yield from self.handle_overflow(
+ inputs, results[0], overflow, inp_ca_ov=inp_ca_ov)
# only do SVP64 dest predicated Rc=1 if dest-pred is not enabled
rc_en = False
self.crl[regnum].eq(cr0)
def do_outregs_nia(self, asmop, ins_name, info, outs,
- carry_en, rc_en, ffirst_hit, ew_dst):
+ ca_en, rc_en, ffirst_hit, ew_dst):
ffirst_hit, vli = ffirst_hit
- # write out any regs for this instruction
- for name, output in outs.items():
- yield from self.check_write(info, name, output, carry_en, ew_dst)
+ # write out any regs for this instruction, but only if fail-first is ok
+ # XXX TODO: allow CR-vector to be written out even if ffirst fails
+ if not ffirst_hit or vli:
+ for name, output in outs.items():
+ yield from self.check_write(info, name, output, ca_en, ew_dst)
# restore the CR value on non-VLI failfirst (from sv.cmp and others
# which write directly to CR in the pseudocode (gah, what a mess)
# if ffirst_hit and not vli:
if op == MicrOp.OP_LOAD.value:
if remap_active:
offsmul = yield self.dec2.in1_step
- log("D-field REMAP src", imm, offsmul)
+ log("D-field REMAP src", imm, offsmul, ldstmode)
else:
offsmul = (srcstep * (subvl+1)) + ssubstep
- log("D-field src", imm, offsmul)
+ log("D-field src", imm, offsmul, ldstmode)
elif op == MicrOp.OP_STORE.value:
# XXX NOTE! no bit-reversed STORE! this should not ever be used
offsmul = (dststep * (subvl+1)) + dsubstep
- log("D-field dst", imm, offsmul)
+ log("D-field dst", imm, offsmul, ldstmode)
# Unit-Strided LD/ST adds offset*width to immediate
if ldstmode == SVP64LDSTmode.UNITSTRIDE.value:
ldst_len = yield self.dec2.e.do.data_len
if name in fregs:
reg_val = SelectableInt(self.fpr(base, is_vec, offs, ew_src))
log("read reg %d/%d: 0x%x" % (base, offs, reg_val.value))
+ self.insnlog.append("rFPR:%d.%d/%d" % (base, offs, ew_src))
elif name is not None:
reg_val = SelectableInt(self.gpr(base, is_vec, offs, ew_src))
+ self.insnlog.append("rGPR:%d.%d/%d" % (base, offs, ew_src))
log("read reg %d/%d: 0x%x" % (base, offs, reg_val.value))
else:
log('zero input reg %s %s' % (name, str(regnum)), is_vec)
if name == 'CR0': # ignore, done already (above)
return
if isinstance(output, int):
- output = SelectableInt(output, 256)
+ output = SelectableInt(output, EFFECTIVELY_UNLIMITED)
# write carry flafs
if name in ['CA', 'CA32']:
if carry_en:
# check zeroing due to predicate bit being zero
if self.is_svp64_mode and self.pred_dst_zero:
log('zeroing reg %s %s' % (str(regnum), str(output)), is_vec)
- output = SelectableInt(0, 256)
+ output = SelectableInt(0, EFFECTIVELY_UNLIMITED)
log("write reg %s%s 0x%x ew %d" % (reg_prefix, str(regnum),
output.value, ew_dst),
kind=LogKind.InstrInOuts)
# zero-extend tov64 bit begore storing (should use EXT oh well)
if output.bits > 64:
output = SelectableInt(output.value, 64)
+ rnum, base, offset = regnum
if name in fregs:
self.fpr.write(regnum, output, is_vec, ew_dst)
+ self.insnlog.append("wFPR:%d.%d/%d" % (rnum, offset, ew_dst))
else:
self.gpr.write(regnum, output, is_vec, ew_dst)
+ self.insnlog.append("wGPR:%d.%d/%d" % (rnum, offset, ew_dst))
def check_step_increment(self, rc_en, asmop, ins_name):
# check if it is the SVSTATE.src/dest step that needs incrementing
projects / openpower-isa.git / blobdiff