SVP64LDSTmode, SVP64PredCR,
SVP64PredInt, SVP64PredMode,
SVP64RMMode, SVPType, XER_bits,
- insns, spr_byname, spr_dict)
+ insns, spr_byname, spr_dict,
+ BFP_FLAG_NAMES)
from openpower.decoder.power_insn import SVP64Instruction
from openpower.decoder.power_svp64 import SVP64RM, decode_extra
from openpower.decoder.selectable_int import (FieldSelectableInt,
from openpower.xer import XERState
from openpower.util import LogKind, log
+LDST_UPDATE_INSNS = ['ldu', 'lwzu', 'lbzu', 'lhzu', 'lhau', 'lfsu', 'lfdu',
+ ]
+
instruction_info = namedtuple('instruction_info',
'func read_regs uninit_regs write_regs ' +
'special_regs op_fields form asmregs')
'XLEN': 64 # elwidth overrides
})
+ for name in BFP_FLAG_NAMES:
+ setattr(self, name, 0)
+
# update pc to requested start point
self.set_pc(initial_pc)
def execute_one(self):
"""execute one instruction
"""
+ self.insnlog = [] # log the instruction
# get the disassembly code for this instruction
if not self.disassembly:
code = yield from self.get_assembly_name()
offs, dbg = 4, "svp64 "
code = self.disassembly[self._pc+offs]
log(" %s sim-execute" % dbg, hex(self._pc), code)
+ self.insnlog.append(code)
opname = code.split(' ')[0]
try:
yield from self.call(opname) # execute the instruction
# not supported yet:
raise e # ... re-raise
+ # append the log file
+ with open("/tmp/insnlog.txt", "a+") as f:
+ f.write(" ".join(self.insnlog)+"\n")
+
log("gprs after code", code)
self.gpr.dump()
crs = []
# list of instructions not being supported by binutils (.long)
dotstrp = asmop[:-1] if asmop[-1] == '.' else asmop
if dotstrp in [*FPTRANS_INSNS,
+ *LDST_UPDATE_INSNS,
'ffmadds', 'fdmadds', 'ffadds',
'minmax',
'setvl', 'svindex', 'svremap', 'svstep',
if name in fregs:
reg_val = SelectableInt(self.fpr(base, is_vec, offs, ew_src))
log("read reg %d/%d: 0x%x" % (base, offs, reg_val.value))
+ self.insnlog.append("rFPR:%d.%d/%d" % (base, offs, ew_src))
elif name is not None:
reg_val = SelectableInt(self.gpr(base, is_vec, offs, ew_src))
+ self.insnlog.append("rGPR:%d.%d/%d" % (base, offs, ew_src))
log("read reg %d/%d: 0x%x" % (base, offs, reg_val.value))
else:
log('zero input reg %s %s' % (name, str(regnum)), is_vec)
# zero-extend tov64 bit begore storing (should use EXT oh well)
if output.bits > 64:
output = SelectableInt(output.value, 64)
+ rnum, base, offset = regnum
if name in fregs:
self.fpr.write(regnum, output, is_vec, ew_dst)
+ self.insnlog.append("wFPR:%d.%d/%d" % (rnum, offset, ew_dst))
else:
self.gpr.write(regnum, output, is_vec, ew_dst)
+ self.insnlog.append("wGPR:%d.%d/%d" % (rnum, offset, ew_dst))
def check_step_increment(self, rc_en, asmop, ins_name):
# check if it is the SVSTATE.src/dest step that needs incrementing