dec2.dec.RT)
if out_sel == OutSel.RT.value:
return out, o_isvec
+ elif name == 'RT_OR_ZERO':
+ log ("get_pdecode_idx_out", out_sel, OutSel.RT.value,
+ OutSel.RT_OR_ZERO.value, out, o_isvec,
+ dec2.dec.RT)
+ if out_sel == OutSel.RT_OR_ZERO.value:
+ return out, o_isvec
elif name == 'FRA':
log ("get_pdecode_idx_out", out_sel, OutSel.FRA.value, out, o_isvec)
if out_sel == OutSel.FRA.value:
SO = self.spr['XER'][XER_bits['SO']]
log("handle_comparison SO", SO)
cr_field = selectconcat(negative, positive, zero, SO)
+ log("handle_comparison cr_field", self.cr, cr_idx, cr_field)
self.crl[cr_idx].eq(cr_field)
def set_pc(self, pc_val):
yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff) # v3.0B suffix
yield self.dec2.sv_rm.eq(sv_rm) # svp64 prefix
yield Settle()
+ # store this for use in get_src_dststeps()
+ self.ldstmode = yield self.dec2.rm_dec.ldstmode
def execute_one(self):
"""execute one instruction
return asmop
def get_remap_indices(self):
+ """WARNING, this function stores remap_idxs and remap_loopends
+ in the class for later use. this to avoid problems with yield
+ """
# go through all iterators in lock-step, advance to next remap_idx
- srcstep, dststep = self.new_srcstep, self.new_dststep
+ srcstep, dststep = self.get_src_dststeps()
# get four SVSHAPEs. here we are hard-coding
SVSHAPE0 = self.spr['SVSHAPE0']
SVSHAPE1 = self.spr['SVSHAPE1']
]
self.remap_loopends = [0] * 4
- self.remap_idxs = [0] * 4
+ self.remap_idxs = [0, 1, 2, 3]
dbg = []
for i, (shape, remap) in enumerate(remaps):
# zero is "disabled"
illegal = False
ins_name = 'setvl'
+ # and svstep not being supported by binutils (.long)
+ if asmop.startswith('svstep'):
+ illegal = False
+ ins_name = 'svstep'
+
# and svremap not being supported by binutils (.long)
if asmop.startswith('svremap'):
illegal = False
self.update_nia()
self.update_pc_next()
return
- srcstep, dststep = self.new_srcstep, self.new_dststep
+ srcstep, dststep = self.get_src_dststeps()
pred_dst_zero = self.pred_dst_zero
pred_src_zero = self.pred_src_zero
vl = self.svstate.vl
reg_val = 0
inputs.append(reg_val)
# arrrrgh, awful hack, to get _RT into namespace
- if ins_name == 'setvl':
+ if ins_name in ['setvl', 'svstep']:
regname = "_RT"
RT = yield self.dec2.dec.RT
self.namespace[regname] = SelectableInt(RT, 5)
+ if RT == 0:
+ self.namespace["RT"] = SelectableInt(0, 5)
+ regnum, is_vec = yield from get_pdecode_idx_out(self.dec2, "RT")
+ log('hack input reg %s %s' % (name, str(regnum)), is_vec)
# in SVP64 mode for LD/ST work out immediate
# XXX TODO: replace_ds for DS-Form rather than D-Form.
log ("bitrev SVD", imm)
replace_d = True
else:
- imm = yield self.dec2.dec.fields.FormD.D[0:16]
+ if info.form == 'DS':
+ # DS-Form, multiply by 4 then knock 2 bits off after
+ imm = yield self.dec2.dec.fields.FormDS.DS[0:14] * 4
+ else:
+ imm = yield self.dec2.dec.fields.FormD.D[0:16]
imm = exts(imm, 16) # sign-extend to integer
# get the right step. LD is from srcstep, ST is dststep
op = yield self.dec2.e.do.insn_type
offsmul = 0
if op == MicrOp.OP_LOAD.value:
- offsmul = srcstep
- log("D-field src", imm, offsmul)
+ if remap_active:
+ offsmul = yield self.dec2.in1_step
+ log("D-field REMAP src", imm, offsmul)
+ else:
+ offsmul = srcstep
+ log("D-field src", imm, offsmul)
elif op == MicrOp.OP_STORE.value:
+ # XXX NOTE! no bit-reversed STORE! this should not ever be used
offsmul = dststep
log("D-field dst", imm, offsmul)
- # bit-reverse mode
+ # bit-reverse mode, rev already done through get_src_dst_steps()
if ldstmode == SVP64LDSTmode.BITREVERSE.value:
# manually look up RC, sigh
RC = yield self.dec2.dec.RC[0:5]
RC = self.gpr(RC)
- log ("RC", RC.value, "imm", imm, "offs", bin(offsmul),
- "rev", bin(bitrev(offsmul, vl)))
- imm = SelectableInt((imm * bitrev(offsmul, vl)) << RC.value, 32)
+ log ("LD-BITREVERSE:", "VL", vl,
+ "RC", RC.value, "imm", imm,
+ "offs", bin(offsmul),
+ )
+ imm = SelectableInt((imm * offsmul) << RC.value, 32)
# Unit-Strided LD/ST adds offset*width to immediate
elif ldstmode == SVP64LDSTmode.UNITSTRIDE.value:
ldst_len = yield self.dec2.e.do.data_len
elif ldstmode == SVP64LDSTmode.ELSTRIDE.value:
imm = SelectableInt(imm * offsmul, 32)
replace_d = True
- ldst_ra_vec = yield self.dec2.rm_dec.ldst_ra_vec
- ldst_imz_in = yield self.dec2.rm_dec.ldst_imz_in
- log("LDSTmode", ldstmode, SVP64LDSTmode.BITREVERSE.value,
- offsmul, imm, ldst_ra_vec, ldst_imz_in)
- # new replacement D
+ if replace_d:
+ ldst_ra_vec = yield self.dec2.rm_dec.ldst_ra_vec
+ ldst_imz_in = yield self.dec2.rm_dec.ldst_imz_in
+ log("LDSTmode", SVP64LDSTmode(ldstmode),
+ offsmul, imm, ldst_ra_vec, ldst_imz_in)
+ # new replacement D... errr.. DS
if replace_d:
- self.namespace['D'] = imm
+ if info.form == 'DS':
+ # TODO: assert 2 LSBs are zero?
+ log("DS-Form, TODO, assert 2 LSBs zero?", bin(imm.value))
+ imm.value = imm.value >> 2
+ self.namespace['DS'] = imm
+ else:
+ self.namespace['D'] = imm
# "special" registers
for special in info.special_regs:
if not self.is_svp64_mode or not pred_dst_zero:
if hasattr(self.dec2.e.do, "rc"):
rc_en = yield self.dec2.e.do.rc.rc
- if rc_en:
+ if rc_en and ins_name not in ['svstep']:
regnum, is_vec = yield from get_pdecode_cr_out(self.dec2, "CR0")
self.handle_comparison(results, regnum)
pre = False
post = False
if self.allow_next_step_inc:
- log("SVSTATE_NEXT: inc requested, mode", self.svstate_next_mode)
+ log("SVSTATE_NEXT: inc requested, mode",
+ self.svstate_next_mode, self.allow_next_step_inc)
yield from self.svstate_pre_inc()
pre = yield from self.update_new_svstate_steps()
if pre:
results = [SelectableInt(0, 64)]
self.handle_comparison(results) # CR0
else:
- log ("SVSTATE_NEXT: post-inc")
+ if self.allow_next_step_inc == 2:
+ log ("SVSTATE_NEXT: read")
+ yield from self.svstate_post_inc()
+ else:
+ log ("SVSTATE_NEXT: post-inc")
+ # use actual src/dst-step here to check end, do NOT
+ # use bit-reversed version
srcstep, dststep = self.new_srcstep, self.new_dststep
remaps = self.get_remap_indices()
remap_idxs = self.remap_idxs
vl = self.svstate.vl
end_src = srcstep == vl-1
end_dst = dststep == vl-1
- if not end_src:
- self.svstate.srcstep += SelectableInt(1, 7)
- if not end_dst:
- self.svstate.dststep += SelectableInt(1, 7)
+ if self.allow_next_step_inc != 2:
+ if not end_src:
+ self.svstate.srcstep += SelectableInt(1, 7)
+ if not end_dst:
+ self.svstate.dststep += SelectableInt(1, 7)
self.namespace['SVSTATE'] = self.svstate.spr
# set CR0 (if Rc=1) based on end
if rc_en:
self.update_pc_next()
- def SVSTATE_NEXT(self, mode):
+ def SVSTATE_NEXT(self, mode, submode):
"""explicitly moves srcstep/dststep on to next element, for
"Vertical-First" mode. this function is called from
setvl pseudo-code, as a pseudo-op "svstep"
+
+ WARNING: this function uses information that was created EARLIER
+ due to it being in the middle of a yield, but this function is
+ *NOT* called from yield (it's called from compiled pseudocode).
"""
- log("SVSTATE_NEXT mode", mode)
- self.allow_next_step_inc = True
+ self.allow_next_step_inc = submode.value + 1
+ log("SVSTATE_NEXT mode", mode, submode, self.allow_next_step_inc)
self.svstate_next_mode = mode
if self.svstate_next_mode > 0:
shape_idx = self.svstate_next_mode.value-1
sv_a_nz = yield self.dec2.sv_a_nz
fft_mode = yield self.dec2.use_svp64_fft
in1 = yield self.dec2.e.read_reg1.data
- log ("SVP64: VL, srcstep, dststep, sv_a_nz, in1 fft",
- vl, srcstep, dststep, sv_a_nz, in1, fft_mode)
+ log ("SVP64: VL, srcstep, dststep, sv_a_nz, in1 fft, svp64",
+ vl, srcstep, dststep, sv_a_nz, in1, fft_mode,
+ self.is_svp64_mode)
# get predicate mask
srcmask = dstmask = 0xffff_ffff_ffff_ffff
log (" new srcstep", srcstep)
log (" new dststep", dststep)
+ def get_src_dststeps(self):
+ """gets srcstep and dststep but performs bit-reversal on srcstep if
+ required. use this ONLY to perform calculations, do NOT update
+ SVSTATE with the bit-reversed value of srcstep
+
+ ARGH, had to store self.ldstmode and VL due to yield issues
+ """
+ srcstep, dststep = self.new_srcstep, self.new_dststep
+ if self.is_svp64_mode:
+ if self.ldstmode == SVP64LDSTmode.BITREVERSE.value:
+ vl = self.svstate.vl
+ log ("SRCSTEP-BITREVERSE:", "VL", vl, "srcstep", srcstep,
+ "rev", bin(bitrev(srcstep, vl)))
+ srcstep = bitrev(srcstep, vl)
+
+ return (srcstep, dststep)
+
def update_new_svstate_steps(self):
+ # note, do not get the bit-reversed srcstep here!
srcstep, dststep = self.new_srcstep, self.new_dststep
# update SVSTATE with new srcstep
projects / openpower-isa.git / blobdiff