convert all test_caller*.py to work with pytest/unittest test discovery

[openpower-isa.git] / src / openpower / decoder / isa / caller.py

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index e51d24f62a731e006e0cab22f7ce1615c80964d4..b5d9f5a5955601a0202fb2d4191310bad6432180 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -14,7 +14,7 @@ related bugs:
 """
 
 import re
-from nmigen.back.pysim import Settle
+from nmigen.sim import Settle
 from functools import wraps
 from copy import copy, deepcopy
 from openpower.decoder.orderedset import OrderedSet
@@ -1263,7 +1263,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
 
         # nop has to be supported, we could let the actual op calculate
         # but PowerDecoder has a pattern for nop
-        if ins_name is 'nop':
+        if ins_name == 'nop':
             self.update_pc_next()
             return
 
@@ -1332,9 +1332,9 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
         # main input registers (RT, RA ...)
         inputs = []
         for name in input_names:
-            print("name", name)
+            log("name", name)
             regval = (yield from self.get_input(name))
-            print("regval", regval)
+            log("regval", regval)
             inputs.append(regval)
 
         # arrrrgh, awful hack, to get _RT into namespace
@@ -1663,7 +1663,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
                     shape_idx = self.svstate_next_mode.value-1
                     endings = self.remap_loopends[shape_idx]
                 cr_field = SelectableInt((~endings) << 1 | endtest, 4)
-                print("svstep Rc=1, CR0", cr_field)
+                log("svstep Rc=1, CR0", cr_field)
                 self.crl[0].eq(cr_field)  # CR0
             if end_src or end_dst:
                 # reset at end of loop including exit Vertical Mode
@@ -1868,14 +1868,6 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
         log("    out_vec", out_vec)
         log("    in_vec", in_vec)
         log("    sv_ptype", sv_ptype, sv_ptype == SVPtype.P2.value)
-        # check if srcstep needs incrementing by one, stop PC advancing
-        # svp64 loop can end early if the dest is scalar for single-pred
-        # but for 2-pred both src/dest have to be checked.
-        # XXX this might not be true! it may just be LD/ST
-        if sv_ptype == SVPtype.P2.value:
-            svp64_is_vector = (out_vec or in_vec)
-        else:
-            svp64_is_vector = out_vec
         # check if this was an sv.bc* and if so did it succeed
         if self.is_svp64_mode and insn_name.startswith("sv.bc"):
             end_loop = self.namespace['end_loop']
@@ -1884,6 +1876,13 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
                 self.svp64_reset_loop()
                 self.update_pc_next()
                 return False
+        # check if srcstep needs incrementing by one, stop PC advancing
+        # but for 2-pred both src/dest have to be checked.
+        # XXX this might not be true! it may just be LD/ST
+        if sv_ptype == SVPtype.P2.value:
+            svp64_is_vector = (out_vec or in_vec)
+        else:
+            svp64_is_vector = out_vec
         # loops end at the first "hit" (source or dest)
         loopend = ((srcstep == vl-1 and ssubstep == subvl) or
                    (dststep == vl-1 and dsubstep == subvl))