from openpower.decoder.isa.radixmmu import RADIX
from openpower.decoder.isa.mem import Mem, swap_order, MemException
from openpower.decoder.isa.svshape import SVSHAPE
+from openpower.decoder.isa.svstate import SVP64State
+
from openpower.util import log
namespace['NIA'] = self.NIA
-# Simple-V: see https://libre-soc.org/openpower/sv
-class SVP64State:
- def __init__(self, init=0):
- self.spr = SelectableInt(init, 32)
- # fields of SVSTATE, see https://libre-soc.org/openpower/sv/sprs/
- self.maxvl = FieldSelectableInt(self.spr, tuple(range(0,7)))
- self.vl = FieldSelectableInt(self.spr, tuple(range(7,14)))
- self.srcstep = FieldSelectableInt(self.spr, tuple(range(14,21)))
- self.dststep = FieldSelectableInt(self.spr, tuple(range(21,28)))
- self.subvl = FieldSelectableInt(self.spr, tuple(range(28,30)))
- self.svstep = FieldSelectableInt(self.spr, tuple(range(30,32)))
-
-
# SVP64 ReMap field
class SVP64RMFields:
def __init__(self, init=0):
if name == 'FRS':
int_op = yield dec2.dec.op.internal_op
fft_en = yield dec2.use_svp64_fft
- if int_op == MicrOp.OP_FP_MADD.value and fft_en:
+ #if int_op == MicrOp.OP_FP_MADD.value and fft_en:
+ if fft_en:
log ("get_pdecode_idx_out2", out_sel, OutSel.FRS.value,
out, o_isvec)
return out, o_isvec
'memassign': self.memassign,
'NIA': self.pc.NIA,
'CIA': self.pc.CIA,
- 'SVSTATE': self.svstate.spr,
+ 'SVSTATE': self.svstate,
'SVSHAPE0': self.spr['SVSHAPE0'],
'SVSHAPE1': self.spr['SVSHAPE1'],
'SVSHAPE2': self.spr['SVSHAPE2'],
# then "yield" fields only from op_fields rather than hard-coded
# list, here.
fields = self.decoder.sigforms[formname]
+ log("prep_namespace", formname, op_fields)
for name in op_fields:
if name == 'spr':
sig = getattr(fields, name.upper())
self.namespace['CA32'] = self.spr['XER'][XER_bits['CA32']].value
# add some SVSTATE convenience variables
- vl = self.svstate.vl.asint(msb0=True)
- srcstep = self.svstate.srcstep.asint(msb0=True)
+ vl = self.svstate.vl
+ srcstep = self.svstate.srcstep
self.namespace['VL'] = vl
self.namespace['srcstep'] = srcstep
yield self.dec2.state.msr.eq(self.msr.value)
yield self.dec2.state.pc.eq(pc)
if self.svstate is not None:
- yield self.dec2.state.svstate.eq(self.svstate.spr.value)
+ yield self.dec2.state.svstate.eq(self.svstate.value)
# SVP64. first, check if the opcode is EXT001, and SVP64 id bits set
yield Settle()
self.pc.update_nia(self.is_svp64_mode)
yield self.dec2.is_svp64_mode.eq(self.is_svp64_mode) # set SVP64 decode
self.namespace['NIA'] = self.pc.NIA
- self.namespace['SVSTATE'] = self.svstate.spr
+ self.namespace['SVSTATE'] = self.svstate
if not self.is_svp64_mode:
return
# in SVP64 mode. decode/print out svp64 prefix, get v3.0B instruction
log ("svp64.rm", bin(pfx.rm.asint(msb0=True)))
- log (" svstate.vl", self.svstate.vl.asint(msb0=True))
- log (" svstate.mvl", self.svstate.maxvl.asint(msb0=True))
+ log (" svstate.vl", self.svstate.vl)
+ log (" svstate.mvl", self.svstate.maxvl)
sv_rm = pfx.rm.asint(msb0=True)
ins = self.imem.ld(pc+4, 4, False, True, instr_fetch=True)
log(" svsetup: 0x%x 0x%x %s" % (pc+4, ins & 0xffffffff, bin(ins)))
illegal = False
name = 'svremap'
+ # and svshape not being supported by binutils (.long)
+ if asmop.startswith('svshape'):
+ illegal = False
+ name = 'svshape'
+
+ # and fsin and fcos
+ if asmop == 'fsins':
+ illegal = False
+ name = 'fsins'
+ if asmop == 'fcoss':
+ illegal = False
+ name = 'fcoss'
+
# sigh also deal with ffmadds not being supported by binutils (.long)
if asmop == 'ffmadds':
illegal = False
name = 'ffmadds'
+ # and ffadds not being supported by binutils (.long)
+ if asmop == 'ffadds':
+ illegal = False
+ name = 'ffadds'
+
if illegal:
print("illegal", name, asmop)
self.call_trap(0x700, PIb.ILLEG)
# preserve order of register names
input_names = create_args(list(info.read_regs) +
list(info.uninit_regs))
- log(input_names)
+ log("input names", input_names)
# get SVP64 entry for the current instruction
sv_rm = self.svp64rm.instrs.get(name)
srcstep, dststep = self.new_srcstep, self.new_dststep
pred_dst_zero = self.pred_dst_zero
pred_src_zero = self.pred_src_zero
- vl = self.svstate.vl.asint(msb0=True)
+ vl = self.svstate.vl
# VL=0 in SVP64 mode means "do nothing: skip instruction"
if self.is_svp64_mode and vl == 0:
self.namespace['NIA'])
return
- # for when SVSHAPE is active, a very bad hack here (to be replaced)
- # using pre-arranged schedule. all of this is awful but it is a
- # start. next job will be to put the proper activation in place
- yield self.dec2.remap_active.eq(1 if self.last_op_svshape else 0)
- if self.is_svp64_mode and self.last_op_svshape:
+ # for when SVREMAP is active, using pre-arranged schedule.
+ # note: modifying PowerDecoder2 needs to "settle"
+ remap_en = self.svstate.SVme
+ persist = self.svstate.RMpst
+ active = (persist or self.last_op_svshape) and remap_en != 0
+ yield self.dec2.remap_active.eq(remap_en if active else 0)
+ yield Settle()
+ if self.is_svp64_mode and (persist or self.last_op_svshape):
# get four SVSHAPEs. here we are hard-coding
- # SVSHAPE0 to FRT, SVSHAPE1 to FRA, SVSHAPE2 to FRC and
- # SVSHAPE3 to FRB, assuming "fmadd FRT, FRA, FRC, FRB."
SVSHAPE0 = self.spr['SVSHAPE0']
SVSHAPE1 = self.spr['SVSHAPE1']
SVSHAPE2 = self.spr['SVSHAPE2']
SVSHAPE3 = self.spr['SVSHAPE3']
+ # just some convenient debug info
for i in range(4):
sname = 'SVSHAPE%d' % i
shape = self.spr[sname]
- print (sname, bin(shape.value))
- print (" lims", shape.lims)
- print (" mode", shape.mode)
- print (" skip", shape.skip)
-
+ log (sname, bin(shape.value))
+ log (" lims", shape.lims)
+ log (" mode", shape.mode)
+ log (" skip", shape.skip)
+
+ # set up the list of steps to remap
+ mi0 = self.svstate.mi0
+ mi1 = self.svstate.mi1
+ mi2 = self.svstate.mi2
+ mo0 = self.svstate.mo0
+ mo1 = self.svstate.mo1
+ steps = [(self.dec2.in1_step, mi0), # RA
+ (self.dec2.in2_step, mi1), # RB
+ (self.dec2.in3_step, mi2), # RC
+ (self.dec2.o_step, mo0), # RT
+ (self.dec2.o2_step, mo1), # EA
+ ]
+ # set up the iterators
remaps = [(SVSHAPE0, SVSHAPE0.get_iterator()),
(SVSHAPE1, SVSHAPE1.get_iterator()),
(SVSHAPE2, SVSHAPE2.get_iterator()),
(SVSHAPE3, SVSHAPE3.get_iterator()),
]
- rremaps = []
+ # go through all iterators in lock-step, advance to next remap_idx
+ remap_idxs = []
for i, (shape, remap) in enumerate(remaps):
# zero is "disabled"
if shape.value == 0x0:
- continue
- # XXX hardcoded! pick dststep for out (i==0) else srcstep
- if shape.mode == 0b00: # multiply mode
- step = dststep if (i == 0) else srcstep
- if shape.mode == 0b01: # FFT butterfly mode
- step = srcstep # XXX HACK - for now only use srcstep
+ remap_idxs.append(0)
+ # pick src or dststep depending on reg num (0-2=in, 3-4=out)
+ step = dststep if (i in [3, 4]) else srcstep
# this is terrible. O(N^2) looking for the match. but hey.
for idx, remap_idx in enumerate(remap):
if idx == step:
break
- # multiply mode
- if shape.mode == 0b00:
- if i == 0:
- yield self.dec2.o_step.eq(remap_idx) # RT
- yield self.dec2.o2_step.eq(remap_idx) # EA
- elif i == 1:
- yield self.dec2.in1_step.eq(remap_idx) # RA
- elif i == 2:
- yield self.dec2.in3_step.eq(remap_idx) # RB
- elif i == 3:
- yield self.dec2.in2_step.eq(remap_idx) # RC
- # FFT butterfly mode
- if shape.mode == 0b01:
- if i == 0:
- yield self.dec2.o_step.eq(remap_idx) # RT
- yield self.dec2.in2_step.eq(remap_idx) # RB
- elif i == 1:
- yield self.dec2.in1_step.eq(remap_idx) # RA
- yield self.dec2.o2_step.eq(remap_idx) # EA (FRS)
- elif i == 2:
- yield self.dec2.in3_step.eq(remap_idx) # RC
- elif i == 3:
- pass # no SVSHAPE3
- rremaps.append((shape.mode, i, idx, remap_idx)) # debug printing
+ remap_idxs.append(remap_idx)
+
+ rremaps = []
+ # now cross-index the required SHAPE for each of 3-in 2-out regs
+ rnames = ['RA', 'RB', 'RC', 'RT', 'EA']
+ for i, (dstep, shape_idx) in enumerate(steps):
+ (shape, remap) = remaps[shape_idx]
+ remap_idx = remap_idxs[shape_idx]
+ # zero is "disabled"
+ if shape.value == 0x0:
+ continue
+ # now set the actual requested step to the current index
+ yield dstep.eq(remap_idx)
+
+ # debug printout info
+ rremaps.append((shape.mode, i, rnames[i], step, shape_idx,
+ remap_idx))
for x in rremaps:
- print ("shape remap", x)
+ log ("shape remap", x)
# after that, settle down (combinatorial) to let Vector reg numbers
# work themselves out
yield Settle()
remap_active = yield self.dec2.remap_active
- print ("remap active", remap_active)
+ log ("remap active", bin(remap_active))
# main input registers (RT, RA ...)
inputs = []
if ldstmode == SVP64LDSTmode.BITREVERSE.value:
imm = yield self.dec2.dec.fields.FormSVD.SVD[0:11]
imm = exts(imm, 11) # sign-extend to integer
- print ("bitrev SVD", imm)
+ log ("bitrev SVD", imm)
replace_d = True
else:
imm = yield self.dec2.dec.fields.FormD.D[0:16]
ftype = 'fpr'
else:
ftype = 'gpr'
- log('writing %s %s %s' % (regnum, ftype, str(output)),
+ log('writing %s %s %s' % (ftype, regnum, str(output)),
is_vec)
if output.bits > 64:
output = SelectableInt(output.value, 64)
yield from self.svstate_pre_inc()
pre = yield from self.update_new_svstate_steps()
if pre:
- log ("SVSTATE_NEXT: end of loop, reset (TODO, update CR0)")
+ # reset at end of loop including exit Vertical Mode
+ log ("SVSTATE_NEXT: end of loop, reset")
self.svp64_reset_loop()
+ self.svstate.vfirst = 0
self.update_nia()
+ if rc_en:
+ results = [SelectableInt(0, 64)]
+ self.handle_comparison(results) # CR0
else:
log ("SVSTATE_NEXT: post-inc")
srcstep, dststep = self.new_srcstep, self.new_dststep
- vl = self.svstate.vl.asint(msb0=True)
+ vl = self.svstate.vl
end_src = srcstep == vl-1
end_dst = dststep == vl-1
if not end_src:
if not end_dst:
self.svstate.dststep += SelectableInt(1, 7)
self.namespace['SVSTATE'] = self.svstate.spr
+ # set CR0 (if Rc=1) based on end
+ if rc_en:
+ srcstep = self.svstate.srcstep
+ dststep = self.svstate.srcstep
+ endtest = 0 if (end_src or end_dst) else 1
+ results = [SelectableInt(endtest, 64)]
+ self.handle_comparison(results) # CR0
if end_src or end_dst:
+ # reset at end of loop including exit Vertical Mode
+ log ("SVSTATE_NEXT: after increments, reset")
self.svp64_reset_loop()
- # TODO: set CR0 (if Rc=1) based on end
+ self.svstate.vfirst = 0
+
elif self.is_svp64_mode:
yield from self.svstate_post_inc()
-
- # XXX only in non-SVP64 mode!
- # record state of whether the current operation was an svshape,
- # to be able to know if it should apply in the next instruction.
- # also (if going to use this instruction) should disable ability
- # to interrupt in between. sigh.
- self.last_op_svshape = asmop == 'svremap'
+ else:
+ # XXX only in non-SVP64 mode!
+ # record state of whether the current operation was an svshape,
+ # to be able to know if it should apply in the next instruction.
+ # also (if going to use this instruction) should disable ability
+ # to interrupt in between. sigh.
+ self.last_op_svshape = asmop == 'svremap'
self.update_pc_next()
"""check if srcstep/dststep need to skip over masked-out predicate bits
"""
# get SVSTATE VL (oh and print out some debug stuff)
- vl = self.svstate.vl.asint(msb0=True)
- srcstep = self.svstate.srcstep.asint(msb0=True)
- dststep = self.svstate.dststep.asint(msb0=True)
+ vl = self.svstate.vl
+ srcstep = self.svstate.srcstep
+ dststep = self.svstate.dststep
sv_a_nz = yield self.dec2.sv_a_nz
fft_mode = yield self.dec2.use_svp64_fft
in1 = yield self.dec2.e.read_reg1.data
srcstep, dststep = self.new_srcstep, self.new_dststep
# update SVSTATE with new srcstep
- self.svstate.srcstep[0:7] = srcstep
- self.svstate.dststep[0:7] = dststep
- self.namespace['SVSTATE'] = self.svstate.spr
- yield self.dec2.state.svstate.eq(self.svstate.spr.value)
+ self.svstate.srcstep = srcstep
+ self.svstate.dststep = dststep
+ self.namespace['SVSTATE'] = self.svstate
+ yield self.dec2.state.svstate.eq(self.svstate.value)
yield Settle() # let decoder update
- srcstep = self.svstate.srcstep.asint(msb0=True)
- dststep = self.svstate.dststep.asint(msb0=True)
- vl = self.svstate.vl.asint(msb0=True)
+ srcstep = self.svstate.srcstep
+ dststep = self.svstate.dststep
+ vl = self.svstate.vl
log (" srcstep", srcstep)
log (" dststep", dststep)
+ log (" vl", vl)
# check if end reached (we let srcstep overrun, above)
# nothing needs doing (TODO zeroing): just do next instruction
def svstate_post_inc(self, vf=0):
# check if SV "Vertical First" mode is enabled
- log (" SV Vertical First", vf, self.msr[MSRb.SVF].value)
- if not vf and self.msr[MSRb.SVF].value == 1:
+ vfirst = self.svstate.vfirst
+ log (" SV Vertical First", vf, vfirst)
+ if not vf and vfirst == 1:
self.update_nia()
return True
# check if it is the SVSTATE.src/dest step that needs incrementing
# this is our Sub-Program-Counter loop from 0 to VL-1
# XXX twin predication TODO
- vl = self.svstate.vl.asint(msb0=True)
- mvl = self.svstate.maxvl.asint(msb0=True)
- srcstep = self.svstate.srcstep.asint(msb0=True)
- dststep = self.svstate.dststep.asint(msb0=True)
+ vl = self.svstate.vl
+ mvl = self.svstate.maxvl
+ srcstep = self.svstate.srcstep
+ dststep = self.svstate.dststep
rm_mode = yield self.dec2.rm_dec.mode
reverse_gear = yield self.dec2.rm_dec.reverse_gear
sv_ptype = yield self.dec2.dec.op.SV_Ptype
self.svstate.dststep += SelectableInt(1, 7)
self.pc.NIA.value = self.pc.CIA.value
self.namespace['NIA'] = self.pc.NIA
- self.namespace['SVSTATE'] = self.svstate.spr
+ self.namespace['SVSTATE'] = self.svstate
log("end of sub-pc call", self.namespace['CIA'],
self.namespace['NIA'])
return False # DO NOT allow PC update whilst Sub-PC loop running
self.namespace['SVSTATE'])
def svp64_reset_loop(self):
- self.svstate.srcstep[0:7] = 0
- self.svstate.dststep[0:7] = 0
+ self.svstate.srcstep = 0
+ self.svstate.dststep = 0
log (" svstate.srcstep loop end (PC to update)")
- self.namespace['SVSTATE'] = self.svstate.spr
+ self.namespace['SVSTATE'] = self.svstate
def update_nia(self):
self.pc.update_nia(self.is_svp64_mode)
context = args[0].namespace # variables to be injected
saved_values = func_globals.copy() # Shallow copy of dict.
+ log("globals before", context.keys())
func_globals.update(context)
result = func(*args, **kwargs)
log("globals after", func_globals['CIA'], func_globals['NIA'])