add nayuki dct

[openpower-isa.git] / src / openpower / decoder / isa / caller.py

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index caa0684de8188631399ab14193c397443a9ba926..c57434cb6a15e7367ca801f81de852ea7bf40534 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1087,6 +1087,14 @@ class ISACaller:
             illegal = False
             name = 'svshape'
 
+        # and fsin and fcos
+        if asmop == 'fsins':
+            illegal = False
+            name = 'fsins'
+        if asmop == 'fcoss':
+            illegal = False
+            name = 'fcoss'
+
         # sigh also deal with ffmadds not being supported by binutils (.long)
         if asmop == 'ffmadds':
             illegal = False
@@ -1154,10 +1162,11 @@ class ISACaller:
         # for when SVREMAP is active, using pre-arranged schedule.
         # note: modifying PowerDecoder2 needs to "settle"
         remap_en = self.svstate.SVme
-        active = self.last_op_svshape and remap_en != 0
+        persist = self.svstate.RMpst
+        active = (persist or self.last_op_svshape) and remap_en != 0
         yield self.dec2.remap_active.eq(remap_en if active else 0)
         yield Settle()
-        if self.is_svp64_mode and self.last_op_svshape:
+        if self.is_svp64_mode and (persist or self.last_op_svshape):
             # get four SVSHAPEs. here we are hard-coding
             SVSHAPE0 = self.spr['SVSHAPE0']
             SVSHAPE1 = self.spr['SVSHAPE1']