sort out subvl unit test with expected results
[openpower-isa.git] / src / openpower / decoder / isa / caller.py
index e592d84d26675a8dd17177501d3e8e8fcc340234..d50165257ac7c56e809fba1b730c43251ed12ffb 100644 (file)
@@ -1142,7 +1142,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
         in the class for later use.  this to avoid problems with yield
         """
         # go through all iterators in lock-step, advance to next remap_idx
-        srcstep, dststep, substep = self.get_src_dststeps()
+        srcstep, dststep, ssubstep = self.get_src_dststeps()
         # get four SVSHAPEs. here we are hard-coding
         SVSHAPE0 = self.spr['SVSHAPE0']
         SVSHAPE1 = self.spr['SVSHAPE1']
@@ -1294,11 +1294,11 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
                 self.update_nia()
                 self.update_pc_next()
                 return
-            srcstep, dststep, substep = self.get_src_dststeps()
+            srcstep, dststep, ssubstep = self.get_src_dststeps()
             pred_dst_zero = self.pred_dst_zero
             pred_src_zero = self.pred_src_zero
             vl = self.svstate.vl
-            subvl = self.svstate.subvl
+            subvl = yield self.dec2.rm_dec.rm_in.subvl
 
         # VL=0 in SVP64 mode means "do nothing: skip instruction"
         if self.is_svp64_mode and vl == 0:
@@ -1331,30 +1331,9 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
         # main input registers (RT, RA ...)
         inputs = []
         for name in input_names:
-            # using PowerDecoder2, first, find the decoder index.
-            # (mapping name RA RB RC RS to in1, in2, in3)
-            regnum, is_vec = yield from get_pdecode_idx_in(self.dec2, name)
-            if regnum is None:
-                # doing this is not part of svp64, it's because output
-                # registers, to be modified, need to be in the namespace.
-                regnum, is_vec = yield from get_pdecode_idx_out(self.dec2, name)
-            if regnum is None:
-                regnum, is_vec = yield from get_pdecode_idx_out2(self.dec2,
-                                                                 name)
-
-            # in case getting the register number is needed, _RA, _RB
-            regname = "_" + name
-            self.namespace[regname] = regnum
-            if not self.is_svp64_mode or not pred_src_zero:
-                log('reading reg %s %s' % (name, str(regnum)), is_vec)
-                if name in fregs:
-                    reg_val = SelectableInt(self.fpr(regnum))
-                elif name is not None:
-                    reg_val = SelectableInt(self.gpr(regnum))
-            else:
-                log('zero input reg %s %s' % (name, str(regnum)), is_vec)
-                reg_val = 0
-            inputs.append(reg_val)
+            regval = (yield from self.get_input(name))
+            inputs.append(regval)
+
         # arrrrgh, awful hack, to get _RT into namespace
         if ins_name in ['setvl', 'svstep']:
             regname = "_RT"
@@ -1368,71 +1347,8 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
         # in SVP64 mode for LD/ST work out immediate
         # XXX TODO: replace_ds for DS-Form rather than D-Form.
         # use info.form to detect
-        replace_d = False  # update / replace constant in pseudocode
         if self.is_svp64_mode:
-            ldstmode = yield self.dec2.rm_dec.ldstmode
-            # shift mode reads SVD (or SVDS - TODO)
-            # *BUT*... because this is "overloading" of LD operations,
-            # it gets *STORED* into D (or DS, TODO)
-            if ldstmode == SVP64LDSTmode.SHIFT.value:
-                imm = yield self.dec2.dec.fields.FormSVD.SVD[0:11]
-                imm = exts(imm, 11)  # sign-extend to integer
-                log("shift SVD", imm)
-                replace_d = True
-            else:
-                if info.form == 'DS':
-                    # DS-Form, multiply by 4 then knock 2 bits off after
-                    imm = yield self.dec2.dec.fields.FormDS.DS[0:14] * 4
-                else:
-                    imm = yield self.dec2.dec.fields.FormD.D[0:16]
-                imm = exts(imm, 16)  # sign-extend to integer
-            # get the right step. LD is from srcstep, ST is dststep
-            op = yield self.dec2.e.do.insn_type
-            offsmul = 0
-            if op == MicrOp.OP_LOAD.value:
-                if remap_active:
-                    offsmul = yield self.dec2.in1_step
-                    log("D-field REMAP src", imm, offsmul)
-                else:
-                    offsmul = (srcstep * (subvl+1)) + substep
-                    log("D-field src", imm, offsmul)
-            elif op == MicrOp.OP_STORE.value:
-                # XXX NOTE! no bit-reversed STORE! this should not ever be used
-                offsmul = (dststep * (subvl+1)) + substep
-                log("D-field dst", imm, offsmul)
-            # bit-reverse mode, rev already done through get_src_dst_steps()
-            if ldstmode == SVP64LDSTmode.SHIFT.value:
-                # manually look up RC, sigh
-                RC = yield self.dec2.dec.RC[0:5]
-                RC = self.gpr(RC)
-                log("LD-SHIFT:", "VL", vl,
-                    "RC", RC.value, "imm", imm,
-                    "offs", bin(offsmul),
-                    )
-                imm = SelectableInt((imm * offsmul) << RC.value, 32)
-            # Unit-Strided LD/ST adds offset*width to immediate
-            elif ldstmode == SVP64LDSTmode.UNITSTRIDE.value:
-                ldst_len = yield self.dec2.e.do.data_len
-                imm = SelectableInt(imm + offsmul * ldst_len, 32)
-                replace_d = True
-            # Element-strided multiplies the immediate by element step
-            elif ldstmode == SVP64LDSTmode.ELSTRIDE.value:
-                imm = SelectableInt(imm * offsmul, 32)
-                replace_d = True
-            if replace_d:
-                ldst_ra_vec = yield self.dec2.rm_dec.ldst_ra_vec
-                ldst_imz_in = yield self.dec2.rm_dec.ldst_imz_in
-                log("LDSTmode", SVP64LDSTmode(ldstmode),
-                    offsmul, imm, ldst_ra_vec, ldst_imz_in)
-        # new replacement D... errr.. DS
-        if replace_d:
-            if info.form == 'DS':
-                # TODO: assert 2 LSBs are zero?
-                log("DS-Form, TODO, assert 2 LSBs zero?", bin(imm.value))
-                imm.value = imm.value >> 2
-                self.namespace['DS'] = imm
-            else:
-                self.namespace['D'] = imm
+            yield from self.check_replace_d(info, remap_active)
 
         # "special" registers
         for special in info.special_regs:
@@ -1530,6 +1446,97 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
         if nia_update:
             self.update_pc_next()
 
+    def check_replace_d(self, info, remap_active):
+        replace_d = False  # update / replace constant in pseudocode
+        ldstmode = yield self.dec2.rm_dec.ldstmode
+        # shift mode reads SVD (or SVDS - TODO)
+        # *BUT*... because this is "overloading" of LD operations,
+        # it gets *STORED* into D (or DS, TODO)
+        if ldstmode == SVP64LDSTmode.SHIFT.value:
+            imm = yield self.dec2.dec.fields.FormSVD.SVD[0:11]
+            imm = exts(imm, 11)  # sign-extend to integer
+            log("shift SVD", imm)
+            replace_d = True
+        else:
+            if info.form == 'DS':
+                # DS-Form, multiply by 4 then knock 2 bits off after
+                imm = yield self.dec2.dec.fields.FormDS.DS[0:14] * 4
+            else:
+                imm = yield self.dec2.dec.fields.FormD.D[0:16]
+            imm = exts(imm, 16)  # sign-extend to integer
+        # get the right step. LD is from srcstep, ST is dststep
+        op = yield self.dec2.e.do.insn_type
+        offsmul = 0
+        if op == MicrOp.OP_LOAD.value:
+            if remap_active:
+                offsmul = yield self.dec2.in1_step
+                log("D-field REMAP src", imm, offsmul)
+            else:
+                offsmul = (srcstep * (subvl+1)) + ssubstep
+                log("D-field src", imm, offsmul)
+        elif op == MicrOp.OP_STORE.value:
+            # XXX NOTE! no bit-reversed STORE! this should not ever be used
+            offsmul = (dststep * (subvl+1)) + ssubstep
+            log("D-field dst", imm, offsmul)
+        # bit-reverse mode, rev already done through get_src_dst_steps()
+        if ldstmode == SVP64LDSTmode.SHIFT.value:
+            # manually look up RC, sigh
+            RC = yield self.dec2.dec.RC[0:5]
+            RC = self.gpr(RC)
+            log("LD-SHIFT:", "VL", vl,
+                "RC", RC.value, "imm", imm,
+                "offs", bin(offsmul),
+                )
+            imm = SelectableInt((imm * offsmul) << RC.value, 32)
+        # Unit-Strided LD/ST adds offset*width to immediate
+        elif ldstmode == SVP64LDSTmode.UNITSTRIDE.value:
+            ldst_len = yield self.dec2.e.do.data_len
+            imm = SelectableInt(imm + offsmul * ldst_len, 32)
+            replace_d = True
+        # Element-strided multiplies the immediate by element step
+        elif ldstmode == SVP64LDSTmode.ELSTRIDE.value:
+            imm = SelectableInt(imm * offsmul, 32)
+            replace_d = True
+        if replace_d:
+            ldst_ra_vec = yield self.dec2.rm_dec.ldst_ra_vec
+            ldst_imz_in = yield self.dec2.rm_dec.ldst_imz_in
+            log("LDSTmode", SVP64LDSTmode(ldstmode),
+                offsmul, imm, ldst_ra_vec, ldst_imz_in)
+        # new replacement D... errr.. DS
+        if replace_d:
+            if info.form == 'DS':
+                # TODO: assert 2 LSBs are zero?
+                log("DS-Form, TODO, assert 2 LSBs zero?", bin(imm.value))
+                imm.value = imm.value >> 2
+                self.namespace['DS'] = imm
+            else:
+                self.namespace['D'] = imm
+
+    def get_input(self, name):
+        # using PowerDecoder2, first, find the decoder index.
+        # (mapping name RA RB RC RS to in1, in2, in3)
+        regnum, is_vec = yield from get_pdecode_idx_in(self.dec2, name)
+        if regnum is None:
+            # doing this is not part of svp64, it's because output
+            # registers, to be modified, need to be in the namespace.
+            regnum, is_vec = yield from get_pdecode_idx_out(self.dec2, name)
+        if regnum is None:
+            regnum, is_vec = yield from get_pdecode_idx_out2(self.dec2, name)
+
+        # in case getting the register number is needed, _RA, _RB
+        regname = "_" + name
+        self.namespace[regname] = regnum
+        if not self.is_svp64_mode or not self.pred_src_zero:
+            log('reading reg %s %s' % (name, str(regnum)), is_vec)
+            if name in fregs:
+                reg_val = SelectableInt(self.fpr(regnum))
+            elif name is not None:
+                reg_val = SelectableInt(self.gpr(regnum))
+        else:
+            log('zero input reg %s %s' % (name, str(regnum)), is_vec)
+            reg_val = 0
+        return reg_val
+
     def remap_debug(self, remaps):
         # just some convenient debug info
         for i in range(4):
@@ -1644,17 +1651,17 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
                 log("SVSTATE_NEXT: post-inc")
             # use actual src/dst-step here to check end, do NOT
             # use bit-reversed version
-            srcstep, dststep, substep = \
-                self.new_srcstep, self.new_dststep, self.new_substep
+            srcstep, dststep, ssubstep = \
+                self.new_srcstep, self.new_dststep, self.new_ssubstep
             remaps = self.get_remap_indices()
             remap_idxs = self.remap_idxs
             vl = self.svstate.vl
-            subvl = self.svstate.subvl
-            end_sub = substep == subvl
+            subvl = yield self.dec2.rm_dec.rm_in.subvl
+            end_sub = ssubstep == subvl
             end_src = srcstep == vl-1
             end_dst = dststep == vl-1
             if self.allow_next_step_inc != 2:
-                self.advance_svstate_steps(end_src, end_dst)
+                yield from self.advance_svstate_steps(end_src, end_dst)
             self.namespace['SVSTATE'] = self.svstate.spr
             # set CR0 (if Rc=1) based on end
             if rc_en:
@@ -1715,19 +1722,21 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
 
     def svstate_pre_inc(self):
         """check if srcstep/dststep need to skip over masked-out predicate bits
+        note that this is not supposed to do anything to substep,
+        it is purely for skipping masked-out bits
         """
         # get SVSTATE VL (oh and print out some debug stuff)
         vl = self.svstate.vl
-        subvl = self.svstate.subvl
+        subvl = yield self.dec2.rm_dec.rm_in.subvl
         srcstep = self.svstate.srcstep
         dststep = self.svstate.dststep
-        substep = self.svstate.substep
+        ssubstep = self.svstate.ssubstep
         sv_a_nz = yield self.dec2.sv_a_nz
         fft_mode = yield self.dec2.use_svp64_fft
         in1 = yield self.dec2.e.read_reg1.data
-        log("SVP64: VL, subvl, srcstep, dststep, substep, sv_a_nz, "
+        log("SVP64: VL, subvl, srcstep, dststep, ssubstep, sv_a_nz, "
             "in1 fft, svp64",
-            vl, subvl, srcstep, dststep, substep, sv_a_nz, in1, fft_mode,
+            vl, subvl, srcstep, dststep, ssubstep, sv_a_nz, in1, fft_mode,
             self.is_svp64_mode)
 
         # get predicate mask (all 64 bits)
@@ -1748,8 +1757,8 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
             srcmask = dstmask = get_predcr(self.crl, dstpred, vl)
             if sv_ptype == SVPtype.P2.value:
                 srcmask = get_predcr(self.crl, srcpred, vl)
-        # work out if the substeps are completed
-        end_sub = substep == subvl
+        # work out if the ssubsteps are completed
+        substart = ssubstep == 0
         log("    pmode", pmode)
         log("    reverse", reverse_gear)
         log("    ptype", sv_ptype)
@@ -1759,25 +1768,21 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
         log("    dstmask", bin(dstmask))
         log("    pred_sz", bin(pred_src_zero))
         log("    pred_dz", bin(pred_dst_zero))
-        log("    end_sub", end_sub)
+        log("    substart", substart)
 
-        if end_sub:
+        if substart:
             # okaaay, so here we simply advance srcstep (TODO dststep)
             # until the predicate mask has a "1" bit... or we run out of VL
             # let srcstep==VL be the indicator to move to next instruction
             if not pred_src_zero:
                 while (((1 << srcstep) & srcmask) == 0) and (srcstep != vl):
-                    log("      skip", bin(1 << srcstep))
+                    log("      sskip", bin(1 << srcstep))
                     srcstep += 1
             # same for dststep
             if not pred_dst_zero:
                 while (((1 << dststep) & dstmask) == 0) and (dststep != vl):
-                    log("      skip", bin(1 << dststep))
+                    log("      dskip", bin(1 << dststep))
                     dststep += 1
-            # and reset substep back to zero
-            substep = 0
-        else:
-            substep += 1 # advance substep
 
         # now work out if the relevant mask bits require zeroing
         if pred_dst_zero:
@@ -1786,38 +1791,38 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
             pred_src_zero = ((1 << srcstep) & srcmask) == 0
 
         # store new srcstep / dststep
-        self.new_srcstep, self.new_dststep, self.new_substep = \
-                (srcstep, dststep, substep)
+        self.new_srcstep, self.new_dststep, self.new_ssubstep = \
+                (srcstep, dststep, ssubstep)
         self.pred_dst_zero, self.pred_src_zero = pred_dst_zero, pred_src_zero
         log("    new srcstep", srcstep)
         log("    new dststep", dststep)
-        log("    new substep", substep)
+        log("    new ssubstep", ssubstep)
 
     def get_src_dststeps(self):
-        """gets srcstep, dststep, and substep
+        """gets srcstep, dststep, and ssubstep
         """
-        return self.new_srcstep, self.new_dststep, self.new_substep
+        return self.new_srcstep, self.new_dststep, self.new_ssubstep
 
     def update_new_svstate_steps(self):
         # note, do not get the bit-reversed srcstep here!
-        srcstep, dststep, substep = \
-            self.new_srcstep, self.new_dststep, self.new_substep
+        srcstep, dststep, ssubstep = \
+            self.new_srcstep, self.new_dststep, self.new_ssubstep
 
         # update SVSTATE with new srcstep
         self.svstate.srcstep = srcstep
         self.svstate.dststep = dststep
-        self.svstate.substep = substep
+        self.svstate.ssubstep = ssubstep
         self.namespace['SVSTATE'] = self.svstate
         yield self.dec2.state.svstate.eq(self.svstate.value)
         yield Settle()  # let decoder update
         srcstep = self.svstate.srcstep
         dststep = self.svstate.dststep
-        substep = self.svstate.substep
+        ssubstep = self.svstate.ssubstep
         vl = self.svstate.vl
-        subvl = self.svstate.subvl
+        subvl = yield self.dec2.rm_dec.rm_in.subvl
         log("    srcstep", srcstep)
         log("    dststep", dststep)
-        log("    substep", substep)
+        log("    ssubstep", ssubstep)
         log("         vl", vl)
         log("      subvl", subvl)
 
@@ -1837,11 +1842,11 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
         # this is our Sub-Program-Counter loop from 0 to VL-1
         # XXX twin predication TODO
         vl = self.svstate.vl
-        subvl = self.svstate.subvl
+        subvl = yield self.dec2.rm_dec.rm_in.subvl
         mvl = self.svstate.maxvl
         srcstep = self.svstate.srcstep
         dststep = self.svstate.dststep
-        substep = self.svstate.substep
+        ssubstep = self.svstate.ssubstep
         rm_mode = yield self.dec2.rm_dec.mode
         reverse_gear = yield self.dec2.rm_dec.reverse_gear
         sv_ptype = yield self.dec2.dec.op.SV_Ptype
@@ -1849,10 +1854,10 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
         in_vec = not (yield self.dec2.no_in_vec)
         log("    svstate.vl", vl)
         log("    svstate.mvl", mvl)
-        log("    svstate.subvl", subvl)
+        log("         rm.subvl", subvl)
         log("    svstate.srcstep", srcstep)
         log("    svstate.dststep", dststep)
-        log("    svstate.substep", substep)
+        log("    svstate.ssubstep", ssubstep)
         log("    mode", rm_mode)
         log("    reverse", reverse_gear)
         log("    out_vec", out_vec)
@@ -1874,8 +1879,9 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
                 self.svp64_reset_loop()
                 self.update_pc_next()
                 return False
-        if svp64_is_vector and srcstep != vl-1 and dststep != vl-1:
-            self.advance_svstate_steps()
+        loopend = (srcstep == vl-1 or dststep == vl-1) and ssubstep == subvl
+        if svp64_is_vector and not loopend:
+            yield from self.advance_svstate_steps()
             self.namespace['SVSTATE'] = self.svstate
             # not an SVP64 branch, so fix PC (NIA==CIA) for next loop
             # (by default, NIA is CIA+4 if v3.0B or CIA+8 if SVP64)
@@ -1893,17 +1899,17 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
         return True
 
     def advance_svstate_steps(self, end_src=False, end_dst=False):
-        subvl = self.svstate.subvl
-        substep = self.svstate.substep
-        end_sub = substep == subvl
+        subvl = yield self.dec2.rm_dec.rm_in.subvl
+        ssubstep = self.svstate.ssubstep
+        end_sub = ssubstep == subvl
         if end_sub:
             if not end_src:
                 self.svstate.srcstep += SelectableInt(1, 7)
             if not end_dst:
                 self.svstate.dststep += SelectableInt(1, 7)
-            self.svstate.substep = SelectableInt(0, 2)
+            self.svstate.ssubstep = SelectableInt(0, 2)
         else:
-            self.svstate.substep += SelectableInt(1, 2) # advance substep
+            self.svstate.ssubstep += SelectableInt(1, 2) # advance ssubstep
 
     def update_pc_next(self):
         # UPDATE program counter
@@ -1916,7 +1922,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
     def svp64_reset_loop(self):
         self.svstate.srcstep = 0
         self.svstate.dststep = 0
-        self.svstate.substep = 0
+        self.svstate.ssubstep = 0
         log("    svstate.srcstep loop end (PC to update)")
         self.namespace['SVSTATE'] = self.svstate