selectconcat)
from openpower.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
insns, MicrOp, In1Sel, In2Sel, In3Sel,
- OutSel, CROutSel,
+ OutSel, CRInSel, CROutSel, LDSTMode,
SVP64RMMode, SVP64PredMode,
- SVP64PredInt, SVP64PredCR)
+ SVP64PredInt, SVP64PredCR,
+ SVP64LDSTmode)
from openpower.decoder.power_enums import SVPtype
-from openpower.decoder.helpers import exts, gtu, ltu, undefined
+from openpower.decoder.helpers import (exts, gtu, ltu, undefined,
+ ISACallerHelper, ISAFPHelpers)
from openpower.consts import PIb, MSRb # big-endian (PowerISA versions)
-from openpower.consts import SVP64CROffs
+from openpower.consts import (SVP64MODE,
+ SVP64CROffs,
+ )
from openpower.decoder.power_svp64 import SVP64RM, decode_extra
from openpower.decoder.isa.radixmmu import RADIX
from openpower.decoder.isa.mem import Mem, swap_order, MemException
+from openpower.decoder.isa.svshape import SVSHAPE
+from openpower.decoder.isa.svstate import SVP64State
+
+
+from openpower.util import log
from collections import namedtuple
import math
"RT": 0,
"RA": 0,
"RB": 0,
+ "RC": 0,
"RS": 0,
+ "BI": 0,
"CR": 0,
"LR": 0,
"CTR": 0,
"TAR": 0,
- "CA": 0,
- "CA32": 0,
"MSR": 0,
"SVSTATE": 0,
+ "SVSHAPE0": 0,
+ "SVSHAPE1": 0,
+ "SVSHAPE2": 0,
+ "SVSHAPE3": 0,
- "overflow": 1,
+ "CA": 0,
+ "CA32": 0,
+
+ "overflow": 7, # should definitely be last
}
fregs = ['FRA', 'FRB', 'FRC', 'FRS', 'FRT']
def create_args(reglist, extra=None):
retval = list(OrderedSet(reglist))
- retval.sort(key=lambda reg: REG_SORT_ORDER[reg])
+ retval.sort(key=lambda reg: REG_SORT_ORDER.get(reg, 0))
if extra is not None:
return [extra] + retval
return retval
self.sd = decoder
self.isacaller = isacaller
self.svstate = svstate
- for i in range(32):
+ for i in range(len(regfile)):
self[i] = SelectableInt(regfile[i], 64)
def __call__(self, ridx):
+ if isinstance(ridx, SelectableInt):
+ ridx = ridx.value
return self[ridx]
def set_form(self, form):
self.form = form
+ def __setitem__(self, rnum, value):
+ # rnum = rnum.value # only SelectableInt allowed
+ log("GPR setitem", rnum, value)
+ if isinstance(rnum, SelectableInt):
+ rnum = rnum.value
+ dict.__setitem__(self, rnum, value)
+
def getz(self, rnum):
# rnum = rnum.value # only SelectableInt allowed
- print("GPR getzero?", rnum)
+ log("GPR getzero?", rnum)
if rnum == 0:
return SelectableInt(0, 64)
return self[rnum]
""" XXX currently not used
"""
rnum = self._get_regnum(attr)
- offs = self.svstate.srcstep
- print("GPR getitem", attr, rnum, "srcoffs", offs)
+ log("GPR getitem", attr, rnum)
return self.regfile[rnum]
- def dump(self):
- for i in range(0, len(self), 8):
- s = []
- for j in range(8):
- s.append("%08x" % self[i+j].value)
- s = ' '.join(s)
- print("reg", "%2d" % i, s)
+ def dump(self, printout=True):
+ res = []
+ for i in range(len(self)):
+ res.append(self[i].value)
+ if printout:
+ for i in range(0, len(res), 8):
+ s = []
+ for j in range(8):
+ s.append("%08x" % res[i+j])
+ s = ' '.join(s)
+ print("reg", "%2d" % i, s)
+ return res
class SPR(dict):
self[key] = v
def __getitem__(self, key):
- print("get spr", key)
- print("dict", self.items())
+ log("get spr", key)
+ log("dict", self.items())
# if key in special_sprs get the special spr, otherwise return key
if isinstance(key, SelectableInt):
key = key.value
info = spr_byname[key]
dict.__setitem__(self, key, SelectableInt(0, info.length))
res = dict.__getitem__(self, key)
- print("spr returning", key, res)
+ log("spr returning", key, res)
return res
def __setitem__(self, key, value):
key = key.value
if isinstance(key, int):
key = spr_dict[key].SPR
- print("spr key", key)
+ log("spr key", key)
key = special_sprs.get(key, key)
if key == 'HSRR0': # HACK!
self.__setitem__('SRR0', value)
if key == 'HSRR1': # HACK!
self.__setitem__('SRR1', value)
- print("setting spr", key, value)
+ log("setting spr", key, value)
dict.__setitem__(self, key, value)
def __call__(self, ridx):
return self[ridx]
+ def dump(self, printout=True):
+ res = []
+ keys = list(self.keys())
+ #keys.sort()
+ for k in keys:
+ sprname = spr_dict.get(k, None)
+ if sprname is None:
+ sprname = k
+ else:
+ sprname = sprname.SPR
+ res.append((sprname, self[k].value))
+ if printout:
+ for sprname, value in res:
+ print(" ", sprname, hex(value))
+ return res
+
class PC:
def __init__(self, pc_init=0):
namespace['NIA'] = self.NIA
-# Simple-V: see https://libre-soc.org/openpower/sv
-class SVP64State:
- def __init__(self, init=0):
- self.spr = SelectableInt(init, 32)
- # fields of SVSTATE, see https://libre-soc.org/openpower/sv/sprs/
- self.maxvl = FieldSelectableInt(self.spr, tuple(range(0,7)))
- self.vl = FieldSelectableInt(self.spr, tuple(range(7,14)))
- self.srcstep = FieldSelectableInt(self.spr, tuple(range(14,21)))
- self.dststep = FieldSelectableInt(self.spr, tuple(range(21,28)))
- self.subvl = FieldSelectableInt(self.spr, tuple(range(28,30)))
- self.svstep = FieldSelectableInt(self.spr, tuple(range(30,32)))
-
-
# SVP64 ReMap field
class SVP64RMFields:
def __init__(self, init=0):
def get_predint(gpr, mask):
r10 = gpr(10)
r30 = gpr(30)
- print ("get_predint", mask, SVP64PredInt.ALWAYS.value)
+ log ("get_predint", mask, SVP64PredInt.ALWAYS.value)
if mask == SVP64PredInt.ALWAYS.value:
return 0xffff_ffff_ffff_ffff
if mask == SVP64PredInt.R3_UNARY.value:
return mask
+# TODO, really should just be using PowerDecoder2
def get_pdecode_idx_in(dec2, name):
op = dec2.dec.op
in1_sel = yield op.in1_sel
in1_isvec = yield dec2.in1_isvec
in2_isvec = yield dec2.in2_isvec
in3_isvec = yield dec2.in3_isvec
- print ("get_pdecode_idx_in in1", name, in1_sel, In1Sel.RA.value,
+ log ("get_pdecode_idx_in in1", name, in1_sel, In1Sel.RA.value,
in1, in1_isvec)
- print ("get_pdecode_idx_in in2", name, in2_sel, In2Sel.RB.value,
+ log ("get_pdecode_idx_in in2", name, in2_sel, In2Sel.RB.value,
in2, in2_isvec)
- print ("get_pdecode_idx_in in3", name, in3_sel, In3Sel.RS.value,
+ log ("get_pdecode_idx_in in3", name, in3_sel, In3Sel.RS.value,
in3, in3_isvec)
- print ("get_pdecode_idx_in FRS in3", name, in3_sel, In3Sel.FRS.value,
+ log ("get_pdecode_idx_in FRS in3", name, in3_sel, In3Sel.FRS.value,
in3, in3_isvec)
- print ("get_pdecode_idx_in FRC in3", name, in3_sel, In3Sel.FRC.value,
+ log ("get_pdecode_idx_in FRB in2", name, in2_sel, In2Sel.FRB.value,
+ in2, in2_isvec)
+ log ("get_pdecode_idx_in FRC in3", name, in3_sel, In3Sel.FRC.value,
in3, in3_isvec)
# identify which regnames map to in1/2/3
if name == 'RA':
return None, False
+# TODO, really should just be using PowerDecoder2
+def get_pdecode_cr_in(dec2, name):
+ op = dec2.dec.op
+ in_sel = yield op.cr_in
+ in_bitfield = yield dec2.dec_cr_in.cr_bitfield.data
+ sv_cr_in = yield op.sv_cr_in
+ spec = yield dec2.crin_svdec.spec
+ sv_override = yield dec2.dec_cr_in.sv_override
+ # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
+ in1 = yield dec2.e.read_cr1.data
+ cr_isvec = yield dec2.cr_in_isvec
+ log ("get_pdecode_cr_in", in_sel, CROutSel.CR0.value, in1, cr_isvec)
+ log (" sv_cr_in", sv_cr_in)
+ log (" cr_bf", in_bitfield)
+ log (" spec", spec)
+ log (" override", sv_override)
+ # identify which regnames map to in / o2
+ if name == 'BI':
+ if in_sel == CRInSel.BI.value:
+ return in1, cr_isvec
+ log ("get_pdecode_cr_in not found", name)
+ return None, False
+
+
+# TODO, really should just be using PowerDecoder2
def get_pdecode_cr_out(dec2, name):
op = dec2.dec.op
out_sel = yield op.cr_out
# get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
out = yield dec2.e.write_cr.data
o_isvec = yield dec2.o_isvec
- print ("get_pdecode_cr_out", out_sel, CROutSel.CR0.value, out, o_isvec)
- print (" sv_cr_out", sv_cr_out)
- print (" cr_bf", out_bitfield)
- print (" spec", spec)
- print (" override", sv_override)
+ log ("get_pdecode_cr_out", out_sel, CROutSel.CR0.value, out, o_isvec)
+ log (" sv_cr_out", sv_cr_out)
+ log (" cr_bf", out_bitfield)
+ log (" spec", spec)
+ log (" override", sv_override)
# identify which regnames map to out / o2
if name == 'CR0':
if out_sel == CROutSel.CR0.value:
return out, o_isvec
- print ("get_pdecode_cr_out not found", name)
+ log ("get_pdecode_cr_out not found", name)
return None, False
+# TODO, really should just be using PowerDecoder2
def get_pdecode_idx_out(dec2, name):
op = dec2.dec.op
out_sel = yield op.out_sel
o_isvec = yield dec2.o_isvec
# identify which regnames map to out / o2
if name == 'RA':
- print ("get_pdecode_idx_out", out_sel, OutSel.RA.value, out, o_isvec)
+ log ("get_pdecode_idx_out", out_sel, OutSel.RA.value, out, o_isvec)
if out_sel == OutSel.RA.value:
return out, o_isvec
elif name == 'RT':
- print ("get_pdecode_idx_out", out_sel, OutSel.RT.value,
- OutSel.RT_OR_ZERO.value, out, o_isvec)
+ log ("get_pdecode_idx_out", out_sel, OutSel.RT.value,
+ OutSel.RT_OR_ZERO.value, out, o_isvec,
+ dec2.dec.RT)
if out_sel == OutSel.RT.value:
return out, o_isvec
+ elif name == 'RT_OR_ZERO':
+ log ("get_pdecode_idx_out", out_sel, OutSel.RT.value,
+ OutSel.RT_OR_ZERO.value, out, o_isvec,
+ dec2.dec.RT)
+ if out_sel == OutSel.RT_OR_ZERO.value:
+ return out, o_isvec
elif name == 'FRA':
- print ("get_pdecode_idx_out", out_sel, OutSel.FRA.value, out, o_isvec)
+ log ("get_pdecode_idx_out", out_sel, OutSel.FRA.value, out, o_isvec)
if out_sel == OutSel.FRA.value:
return out, o_isvec
elif name == 'FRT':
- print ("get_pdecode_idx_out", out_sel, OutSel.FRT.value,
+ log ("get_pdecode_idx_out", out_sel, OutSel.FRT.value,
OutSel.FRT.value, out, o_isvec)
if out_sel == OutSel.FRT.value:
return out, o_isvec
- print ("get_pdecode_idx_out not found", name)
+ log ("get_pdecode_idx_out not found", name, out_sel, out, o_isvec)
return None, False
-# XXX TODO
+# TODO, really should just be using PowerDecoder2
def get_pdecode_idx_out2(dec2, name):
+ # check first if register is activated for write
op = dec2.dec.op
- print ("TODO: get_pdecode_idx_out2", name)
+ out_sel = yield op.out_sel
+ out = yield dec2.e.write_ea.data
+ o_isvec = yield dec2.o2_isvec
+ out_ok = yield dec2.e.write_ea.ok
+ log ("get_pdecode_idx_out2", name, out_sel, out, out_ok, o_isvec)
+ if not out_ok:
+ return None, False
+
+ if name == 'RA':
+ if hasattr(op, "upd"):
+ # update mode LD/ST uses read-reg A also as an output
+ upd = yield op.upd
+ log ("get_pdecode_idx_out2", upd, LDSTMode.update.value,
+ out_sel, OutSel.RA.value,
+ out, o_isvec)
+ if upd == LDSTMode.update.value:
+ return out, o_isvec
+ if name == 'FRS':
+ int_op = yield dec2.dec.op.internal_op
+ fft_en = yield dec2.use_svp64_fft
+ #if int_op == MicrOp.OP_FP_MADD.value and fft_en:
+ if fft_en:
+ log ("get_pdecode_idx_out2", out_sel, OutSel.FRS.value,
+ out, o_isvec)
+ return out, o_isvec
return None, False
-class ISACaller:
+class ISACaller(ISACallerHelper, ISAFPHelpers):
# decoder2 - an instance of power_decoder2
# regfile - a list of initial values for the registers
# initial_{etc} - initial values for SPRs, Condition Register, Mem, MSR
initial_insns = {}
assert self.respect_pc == False, "instructions required to honor pc"
- print("ISACaller insns", respect_pc, initial_insns, disassembly)
- print("ISACaller initial_msr", initial_msr)
+ log("ISACaller insns", respect_pc, initial_insns, disassembly)
+ log("ISACaller initial_msr", initial_msr)
# "fake program counter" mode (for unit testing)
self.fake_pc = 0
for i, code in enumerate(disassembly):
self.disassembly[i*4 + disasm_start] = code
- # set up registers, instruction memory, data memory, PC, SPRs, MSR
+ # set up registers, instruction memory, data memory, PC, SPRs, MSR, CR
self.svp64rm = SVP64RM()
if initial_svstate is None:
initial_svstate = 0
if isinstance(initial_svstate, int):
initial_svstate = SVP64State(initial_svstate)
+ # SVSTATE, MSR and PC
self.svstate = initial_svstate
+ self.msr = SelectableInt(initial_msr, 64) # underlying reg
+ self.pc = PC()
+ # GPR FPR SPR registers
+ initial_sprs = copy(initial_sprs) # so as not to get modified
self.gpr = GPR(decoder2, self, self.svstate, regfile)
self.fpr = GPR(decoder2, self, self.svstate, fpregfile)
self.spr = SPR(decoder2, initial_sprs) # initialise SPRs before MMU
+
+ # set up 4 dummy SVSHAPEs if they aren't already set up
+ for i in range(4):
+ sname = 'SVSHAPE%d' % i
+ if sname not in self.spr:
+ self.spr[sname] = SVSHAPE(0)
+ else:
+ # make sure it's an SVSHAPE
+ val = self.spr[sname].value
+ self.spr[sname] = SVSHAPE(val)
+ self.last_op_svshape = False
+
+ # "raw" memory
self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
# MMU mode, redirect underlying Mem through RADIX
- self.msr = SelectableInt(initial_msr, 64) # underlying reg
if mmu:
self.mem = RADIX(self.mem, self)
if icachemmu:
self.imem = RADIX(self.imem, self)
- self.pc = PC()
# TODO, needed here:
# FPR (same as GPR except for FP nums)
'memassign': self.memassign,
'NIA': self.pc.NIA,
'CIA': self.pc.CIA,
- 'SVSTATE': self.svstate.spr,
+ 'SVSTATE': self.svstate,
+ 'SVSHAPE0': self.spr['SVSHAPE0'],
+ 'SVSHAPE1': self.spr['SVSHAPE1'],
+ 'SVSHAPE2': self.spr['SVSHAPE2'],
+ 'SVSHAPE3': self.spr['SVSHAPE3'],
'CR': self.cr,
'MSR': self.msr,
'undefined': undefined,
'mode_is_64bit': True,
- 'SO': XER_bits['SO']
+ 'SO': XER_bits['SO'],
+ 'XLEN': 64 # elwidth overrides, later
})
# update pc to requested start point
hence the default arguments. when calling from inside ISACaller
it is best to use call_trap()
"""
- print("TRAP:", hex(trap_addr), hex(self.namespace['MSR'].value))
+ log("TRAP:", hex(trap_addr), hex(self.namespace['MSR'].value))
# store CIA(+4?) in SRR0, set NIA to 0x700
# store MSR in SRR1, set MSR to um errr something, have to check spec
# store SVSTATE (if enabled) in SVSRR0
def memassign(self, ea, sz, val):
self.mem.memassign(ea, sz, val)
- def prep_namespace(self, formname, op_fields):
+ def prep_namespace(self, insn_name, formname, op_fields):
# TODO: get field names from form in decoder*1* (not decoder2)
# decoder2 is hand-created, and decoder1.sigform is auto-generated
# from spec
# then "yield" fields only from op_fields rather than hard-coded
# list, here.
fields = self.decoder.sigforms[formname]
+ log("prep_namespace", formname, op_fields)
for name in op_fields:
- if name == 'spr':
- sig = getattr(fields, name.upper())
- else:
+ # CR immediates. deal with separately. needs modifying
+ # pseudocode
+ if self.is_svp64_mode and name in ['BI']: # TODO, more CRs
+ # BI is a 5-bit, must reconstruct the value
+ regnum, is_vec = yield from get_pdecode_cr_in(self.dec2, name)
sig = getattr(fields, name)
- val = yield sig
+ val = yield sig
+ # low 2 LSBs (CR field selector) remain same, CR num extended
+ assert regnum <= 7, "sigh, TODO, 128 CR fields"
+ val = (val & 0b11) | (regnum<<2)
+ else:
+ if name == 'spr':
+ sig = getattr(fields, name.upper())
+ else:
+ sig = getattr(fields, name)
+ val = yield sig
# these are all opcode fields involved in index-selection of CR,
# and need to do "standard" arithmetic. CR[BA+32] for example
# would, if using SelectableInt, only be 5-bit.
self.namespace['CA'] = self.spr['XER'][XER_bits['CA']].value
self.namespace['CA32'] = self.spr['XER'][XER_bits['CA32']].value
+ # add some SVSTATE convenience variables
+ vl = self.svstate.vl
+ srcstep = self.svstate.srcstep
+ self.namespace['VL'] = vl
+ self.namespace['srcstep'] = srcstep
+
+ # sv.bc* need some extra fields
+ if self.is_svp64_mode and insn_name.startswith("sv.bc"):
+ # blegh grab bits manually
+ mode = yield self.dec2.rm_dec.rm_in.mode
+ bc_vlset = (mode & SVP64MODE.BC_VLSET) != 0
+ bc_vli = (mode & SVP64MODE.BC_VLI) != 0
+ bc_snz = (mode & SVP64MODE.BC_SNZ) != 0
+ bc_vsb = yield self.dec2.rm_dec.bc_vsb
+ bc_lru = yield self.dec2.rm_dec.bc_lru
+ bc_gate = yield self.dec2.rm_dec.bc_gate
+ sz = yield self.dec2.rm_dec.pred_sz
+ self.namespace['ALL'] = SelectableInt(bc_gate, 1)
+ self.namespace['VSb'] = SelectableInt(bc_vsb, 1)
+ self.namespace['LRu'] = SelectableInt(bc_lru, 1)
+ self.namespace['VLSET'] = SelectableInt(bc_vlset, 1)
+ self.namespace['VLI'] = SelectableInt(bc_vli, 1)
+ self.namespace['sz'] = SelectableInt(sz, 1)
+ self.namespace['SNZ'] = SelectableInt(bc_snz, 1)
+
def handle_carry_(self, inputs, outputs, already_done):
inv_a = yield self.dec2.e.do.invert_in
if inv_a:
imm = yield self.dec2.e.do.imm_data.data
inputs.append(SelectableInt(imm, 64))
assert len(outputs) >= 1
- print("outputs", repr(outputs))
+ log("outputs", repr(outputs))
if isinstance(outputs, list) or isinstance(outputs, tuple):
output = outputs[0]
else:
output = outputs
gts = []
for x in inputs:
- print("gt input", x, output)
+ log("gt input", x, output)
gt = (gtu(x, output))
gts.append(gt)
- print(gts)
+ log(gts)
cy = 1 if any(gts) else 0
- print("CA", cy, gts)
+ log("CA", cy, gts)
if not (1 & already_done):
self.spr['XER'][XER_bits['CA']] = cy
- print("inputs", already_done, inputs)
+ log("inputs", already_done, inputs)
# 32 bit carry
# ARGH... different for OP_ADD... *sigh*...
op = yield self.dec2.e.do.insn_type
else:
b32 = False
cy32 = res32 ^ a32 ^ b32
- print("CA32 ADD", cy32)
+ log("CA32 ADD", cy32)
else:
gts = []
for x in inputs:
- print("input", x, output)
- print(" x[32:64]", x, x[32:64])
- print(" o[32:64]", output, output[32:64])
+ log("input", x, output)
+ log(" x[32:64]", x, x[32:64])
+ log(" o[32:64]", output, output[32:64])
gt = (gtu(x[32:64], output[32:64])) == SelectableInt(1, 1)
gts.append(gt)
cy32 = 1 if any(gts) else 0
- print("CA32", cy32, gts)
+ log("CA32", cy32, gts)
if not (2 & already_done):
self.spr['XER'][XER_bits['CA32']] = cy32
imm = yield self.dec2.e.do.imm_data.data
inputs.append(SelectableInt(imm, 64))
assert len(outputs) >= 1
- print("handle_overflow", inputs, outputs, div_overflow)
+ log("handle_overflow", inputs, outputs, div_overflow)
if len(inputs) < 2 and div_overflow is None:
return
out = outputs[0]
assert isinstance(out, SelectableInt), \
"out zero not a SelectableInt %s" % repr(outputs)
- print("handle_comparison", out.bits, hex(out.value))
+ log("handle_comparison", out.bits, hex(out.value))
# TODO - XXX *processor* in 32-bit mode
# https://bugs.libre-soc.org/show_bug.cgi?id=424
# if is_32bit:
# o32 = exts(out.value, 32)
# print ("handle_comparison exts 32 bit", hex(o32))
out = exts(out.value, out.bits)
- print("handle_comparison exts", hex(out))
+ log("handle_comparison exts", hex(out))
zero = SelectableInt(out == 0, 1)
positive = SelectableInt(out > 0, 1)
negative = SelectableInt(out < 0, 1)
SO = self.spr['XER'][XER_bits['SO']]
- print("handle_comparison SO", SO)
+ log("handle_comparison SO", SO)
cr_field = selectconcat(negative, positive, zero, SO)
+ log("handle_comparison cr_field", self.cr, cr_idx, cr_field)
self.crl[cr_idx].eq(cr_field)
def set_pc(self, pc_val):
self.namespace['NIA'] = SelectableInt(pc_val, 64)
self.pc.update(self.namespace, self.is_svp64_mode)
- def setup_one(self):
- """set up one instruction
+ def get_next_insn(self):
+ """check instruction
"""
if self.respect_pc:
pc = self.pc.CIA.value
else:
pc = self.fake_pc
- self._pc = pc
ins = self.imem.ld(pc, 4, False, True, instr_fetch=True)
if ins is None:
raise KeyError("no instruction at 0x%x" % pc)
- print("setup: 0x%x 0x%x %s" % (pc, ins & 0xffffffff, bin(ins)))
- print("CIA NIA", self.respect_pc, self.pc.CIA.value, self.pc.NIA.value)
+ return pc, ins
+
+ def setup_one(self):
+ """set up one instruction
+ """
+ pc, insn = self.get_next_insn()
+ yield from self.setup_next_insn(pc, insn)
+
+ def setup_next_insn(self, pc, ins):
+ """set up next instruction
+ """
+ self._pc = pc
+ log("setup: 0x%x 0x%x %s" % (pc, ins & 0xffffffff, bin(ins)))
+ log("CIA NIA", self.respect_pc, self.pc.CIA.value, self.pc.NIA.value)
yield self.dec2.sv_rm.eq(0)
yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff)
yield self.dec2.state.msr.eq(self.msr.value)
yield self.dec2.state.pc.eq(pc)
if self.svstate is not None:
- yield self.dec2.state.svstate.eq(self.svstate.spr.value)
+ yield self.dec2.state.svstate.eq(self.svstate.value)
# SVP64. first, check if the opcode is EXT001, and SVP64 id bits set
yield Settle()
pfx = SVP64PrefixFields() # TODO should probably use SVP64PrefixDecoder
pfx.insn.value = opcode
major = pfx.major.asint(msb0=True) # MSB0 inversion
- print ("prefix test: opcode:", major, bin(major),
+ log ("prefix test: opcode:", major, bin(major),
pfx.insn[7] == 0b1, pfx.insn[9] == 0b1)
self.is_svp64_mode = ((major == 0b000001) and
pfx.insn[7].value == 0b1 and
pfx.insn[9].value == 0b1)
self.pc.update_nia(self.is_svp64_mode)
+ yield self.dec2.is_svp64_mode.eq(self.is_svp64_mode) # set SVP64 decode
self.namespace['NIA'] = self.pc.NIA
- self.namespace['SVSTATE'] = self.svstate.spr
+ self.namespace['SVSTATE'] = self.svstate
if not self.is_svp64_mode:
return
# in SVP64 mode. decode/print out svp64 prefix, get v3.0B instruction
- print ("svp64.rm", bin(pfx.rm.asint(msb0=True)))
- print (" svstate.vl", self.svstate.vl.asint(msb0=True))
- print (" svstate.mvl", self.svstate.maxvl.asint(msb0=True))
+ log ("svp64.rm", bin(pfx.rm.asint(msb0=True)))
+ log (" svstate.vl", self.svstate.vl)
+ log (" svstate.mvl", self.svstate.maxvl)
sv_rm = pfx.rm.asint(msb0=True)
ins = self.imem.ld(pc+4, 4, False, True, instr_fetch=True)
- print(" svsetup: 0x%x 0x%x %s" % (pc+4, ins & 0xffffffff, bin(ins)))
+ log(" svsetup: 0x%x 0x%x %s" % (pc+4, ins & 0xffffffff, bin(ins)))
yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff) # v3.0B suffix
yield self.dec2.sv_rm.eq(sv_rm) # svp64 prefix
yield Settle()
"""
# get the disassembly code for this instruction
if self.is_svp64_mode:
- code = self.disassembly[self._pc+4]
- print(" svp64 sim-execute", hex(self._pc), code)
+ if not self.disassembly:
+ code = yield from self.get_assembly_name()
+ else:
+ code = self.disassembly[self._pc+4]
+ log(" svp64 sim-execute", hex(self._pc), code)
else:
- code = self.disassembly[self._pc]
- print("sim-execute", hex(self._pc), code)
+ if not self.disassembly:
+ code = yield from self.get_assembly_name()
+ else:
+ code = self.disassembly[self._pc]
+ log("sim-execute", hex(self._pc), code)
opname = code.split(' ')[0]
try:
yield from self.call(opname) # execute the instruction
if not self.respect_pc:
self.fake_pc += 4
- print("execute one, CIA NIA", self.pc.CIA.value, self.pc.NIA.value)
+ log("execute one, CIA NIA", hex(self.pc.CIA.value),
+ hex(self.pc.NIA.value))
def get_assembly_name(self):
# TODO, asmregs is from the spec, e.g. add RT,RA,RB
insn_1_11 = yield self.dec2.e.do.insn[1:11]
asmcode = yield self.dec2.dec.op.asmcode
int_op = yield self.dec2.dec.op.internal_op
- print("get assembly name asmcode", asmcode, int_op,
+ log("get assembly name asmcode", asmcode, int_op,
hex(dec_insn), bin(insn_1_11))
asmop = insns.get(asmcode, None)
rc_en = False
rc_ok = False
# grrrr have to special-case MUL op (see DecodeOE)
- print("ov %d en %d rc %d en %d op %d" %
+ log("ov %d en %d rc %d en %d op %d" %
(ov_ok, ov_en, rc_ok, rc_en, int_op))
if int_op in [MicrOp.OP_MUL_H64.value, MicrOp.OP_MUL_H32.value]:
- print("mul op")
+ log("mul op")
if rc_en & rc_ok:
asmop += "."
else:
lk = yield self.dec2.e.do.lk
if lk:
asmop += "l"
- print("int_op", int_op)
+ log("int_op", int_op)
if int_op in [MicrOp.OP_B.value, MicrOp.OP_BC.value]:
AA = yield self.dec2.dec.fields.FormI.AA[0:-1]
- print("AA", AA)
+ log("AA", AA)
if AA:
asmop += "a"
spr_msb = yield from self.get_spr_msb()
asmop = 'mtcrf'
return asmop
+ def get_remap_indices(self):
+ """WARNING, this function stores remap_idxs and remap_loopends
+ in the class for later use. this to avoid problems with yield
+ """
+ # go through all iterators in lock-step, advance to next remap_idx
+ srcstep, dststep = self.get_src_dststeps()
+ # get four SVSHAPEs. here we are hard-coding
+ SVSHAPE0 = self.spr['SVSHAPE0']
+ SVSHAPE1 = self.spr['SVSHAPE1']
+ SVSHAPE2 = self.spr['SVSHAPE2']
+ SVSHAPE3 = self.spr['SVSHAPE3']
+ # set up the iterators
+ remaps = [(SVSHAPE0, SVSHAPE0.get_iterator()),
+ (SVSHAPE1, SVSHAPE1.get_iterator()),
+ (SVSHAPE2, SVSHAPE2.get_iterator()),
+ (SVSHAPE3, SVSHAPE3.get_iterator()),
+ ]
+
+ self.remap_loopends = [0] * 4
+ self.remap_idxs = [0, 1, 2, 3]
+ dbg = []
+ for i, (shape, remap) in enumerate(remaps):
+ # zero is "disabled"
+ if shape.value == 0x0:
+ self.remap_idxs[i] = 0
+ # pick src or dststep depending on reg num (0-2=in, 3-4=out)
+ step = dststep if (i in [3, 4]) else srcstep
+ # this is terrible. O(N^2) looking for the match. but hey.
+ for idx, (remap_idx, loopends) in enumerate(remap):
+ if idx == step:
+ break
+ self.remap_idxs[i] = remap_idx
+ self.remap_loopends[i] = loopends
+ dbg.append((i, step, remap_idx, loopends))
+ for (i, step, remap_idx, loopends) in dbg:
+ log ("SVSHAPE %d idx, end" % i, step, remap_idx, bin(loopends))
+ return remaps
+
def get_spr_msb(self):
dec_insn = yield self.dec2.e.do.insn
return dec_insn & (1 << 20) != 0 # sigh - XFF.spr[-1]?
def call(self, name):
"""call(opcode) - the primary execution point for instructions
"""
- name = name.strip() # remove spaces if not already done so
+ self.last_st_addr = None # reset the last known store address
+ self.last_ld_addr = None # etc.
+
+ ins_name = name.strip() # remove spaces if not already done so
if self.halted:
- print("halted - not executing", name)
+ log("halted - not executing", ins_name)
return
# TODO, asmregs is from the spec, e.g. add RT,RA,RB
# see http://bugs.libre-riscv.org/show_bug.cgi?id=282
asmop = yield from self.get_assembly_name()
- print("call", name, asmop)
+ log("call", ins_name, asmop)
# check privileged
int_op = yield self.dec2.dec.op.internal_op
MicrOp.OP_MTSPR.value] and spr_msb:
instr_is_privileged = True
- print("is priv", instr_is_privileged, hex(self.msr.value),
+ log("is priv", instr_is_privileged, hex(self.msr.value),
self.msr[MSRb.PR])
# check MSR priv bit and whether op is privileged: if so, throw trap
if instr_is_privileged and self.msr[MSRb.PR] == 1:
return
# check halted condition
- if name == 'attn':
+ if ins_name == 'attn':
self.halted = True
return
# check illegal instruction
illegal = False
- if name not in ['mtcrf', 'mtocrf']:
- illegal = name != asmop
+ if ins_name not in ['mtcrf', 'mtocrf']:
+ illegal = ins_name != asmop
# sigh deal with setvl not being supported by binutils (.long)
if asmop.startswith('setvl'):
illegal = False
- name = 'setvl'
+ ins_name = 'setvl'
+
+ # and svstep not being supported by binutils (.long)
+ if asmop.startswith('svstep'):
+ illegal = False
+ ins_name = 'svstep'
+
+ # and svremap not being supported by binutils (.long)
+ if asmop.startswith('svremap'):
+ illegal = False
+ ins_name = 'svremap'
+ # and svshape not being supported by binutils (.long)
+ if asmop.startswith('svshape'):
+ illegal = False
+ ins_name = 'svshape'
+
+ # and fsin and fcos
+ if asmop == 'fsins':
+ illegal = False
+ ins_name = 'fsins'
+ if asmop == 'fcoss':
+ illegal = False
+ ins_name = 'fcoss'
+
+ # sigh also deal with ffmadds not being supported by binutils (.long)
+ if asmop == 'ffmadds':
+ illegal = False
+ ins_name = 'ffmadds'
+
+ # and fdmadds not being supported by binutils (.long)
+ if asmop == 'fdmadds':
+ illegal = False
+ ins_name = 'fdmadds'
+
+ # and ffadds not being supported by binutils (.long)
+ if asmop == 'ffadds':
+ illegal = False
+ ins_name = 'ffadds'
+
+ # branch-conditional redirects to sv.bc
+ if asmop.startswith('bc') and self.is_svp64_mode:
+ ins_name = 'sv.%s' % ins_name
+
+ log(" post-processed name", ins_name, asmop)
+
+ # illegal instructions call TRAP at 0x700
if illegal:
- print("illegal", name, asmop)
+ print("illegal", ins_name, asmop)
self.call_trap(0x700, PIb.ILLEG)
print("name %s != %s - calling ILLEGAL trap, PC: %x" %
- (name, asmop, self.pc.CIA.value))
+ (ins_name, asmop, self.pc.CIA.value))
return
- info = self.instrs[name]
- yield from self.prep_namespace(info.form, info.op_fields)
+ # this is for setvl "Vertical" mode: if set true,
+ # srcstep/dststep is explicitly advanced. mode says which SVSTATE to
+ # test for Rc=1 end condition. 3 bits of all 3 loops are put into CR0
+ self.allow_next_step_inc = False
+ self.svstate_next_mode = 0
+
+ # nop has to be supported, we could let the actual op calculate
+ # but PowerDecoder has a pattern for nop
+ if ins_name is 'nop':
+ self.update_pc_next()
+ return
+
+ # look up instruction in ISA.instrs, prepare namespace
+ info = self.instrs[ins_name]
+ yield from self.prep_namespace(ins_name, info.form, info.op_fields)
# preserve order of register names
input_names = create_args(list(info.read_regs) +
list(info.uninit_regs))
- print(input_names)
+ log("input names", input_names)
# get SVP64 entry for the current instruction
- sv_rm = self.svp64rm.instrs.get(name)
+ sv_rm = self.svp64rm.instrs.get(ins_name)
if sv_rm is not None:
dest_cr, src_cr, src_byname, dest_byname = decode_extra(sv_rm)
else:
dest_cr, src_cr, src_byname, dest_byname = False, False, {}, {}
- print ("sv rm", sv_rm, dest_cr, src_cr, src_byname, dest_byname)
+ log ("sv rm", sv_rm, dest_cr, src_cr, src_byname, dest_byname)
- # get SVSTATE VL (oh and print out some debug stuff)
+ # see if srcstep/dststep need skipping over masked-out predicate bits
+ if (self.is_svp64_mode or ins_name == 'setvl' or
+ ins_name in ['svremap', 'svstate']):
+ yield from self.svstate_pre_inc()
if self.is_svp64_mode:
- vl = self.svstate.vl.asint(msb0=True)
- srcstep = self.svstate.srcstep.asint(msb0=True)
- dststep = self.svstate.dststep.asint(msb0=True)
- sv_a_nz = yield self.dec2.sv_a_nz
- in1 = yield self.dec2.e.read_reg1.data
- print ("SVP64: VL, srcstep, dststep, sv_a_nz, in1",
- vl, srcstep, dststep, sv_a_nz, in1)
-
- # get predicate mask
- srcmask = dstmask = 0xffff_ffff_ffff_ffff
- if self.is_svp64_mode:
- pmode = yield self.dec2.rm_dec.predmode
- sv_ptype = yield self.dec2.dec.op.SV_Ptype
- srcpred = yield self.dec2.rm_dec.srcpred
- dstpred = yield self.dec2.rm_dec.dstpred
- pred_src_zero = yield self.dec2.rm_dec.pred_sz
- pred_dst_zero = yield self.dec2.rm_dec.pred_dz
- if pmode == SVP64PredMode.INT.value:
- srcmask = dstmask = get_predint(self.gpr, dstpred)
- if sv_ptype == SVPtype.P2.value:
- srcmask = get_predint(self.gpr, srcpred)
- elif pmode == SVP64PredMode.CR.value:
- srcmask = dstmask = get_predcr(self.crl, dstpred, vl)
- if sv_ptype == SVPtype.P2.value:
- srcmask = get_predcr(self.crl, srcpred, vl)
- print (" pmode", pmode)
- print (" ptype", sv_ptype)
- print (" srcpred", bin(srcpred))
- print (" dstpred", bin(dstpred))
- print (" srcmask", bin(srcmask))
- print (" dstmask", bin(dstmask))
- print (" pred_sz", bin(pred_src_zero))
- print (" pred_dz", bin(pred_dst_zero))
-
- # okaaay, so here we simply advance srcstep (TODO dststep)
- # until the predicate mask has a "1" bit... or we run out of VL
- # let srcstep==VL be the indicator to move to next instruction
- if not pred_src_zero:
- while (((1<<srcstep) & srcmask) == 0) and (srcstep != vl):
- print (" skip", bin(1<<srcstep))
- srcstep += 1
- # same for dststep
- if not pred_dst_zero:
- while (((1<<dststep) & dstmask) == 0) and (dststep != vl):
- print (" skip", bin(1<<dststep))
- dststep += 1
-
- # now work out if the relevant mask bits require zeroing
- if pred_dst_zero:
- pred_dst_zero = ((1<<dststep) & dstmask) == 0
- if pred_src_zero:
- pred_src_zero = ((1<<srcstep) & srcmask) == 0
-
- # update SVSTATE with new srcstep
- self.svstate.srcstep[0:7] = srcstep
- self.svstate.dststep[0:7] = dststep
- self.namespace['SVSTATE'] = self.svstate.spr
- yield self.dec2.state.svstate.eq(self.svstate.spr.value)
- yield Settle() # let decoder update
- srcstep = self.svstate.srcstep.asint(msb0=True)
- dststep = self.svstate.dststep.asint(msb0=True)
- print (" srcstep", srcstep)
- print (" dststep", dststep)
-
- # check if end reached (we let srcstep overrun, above)
- # nothing needs doing (TODO zeroing): just do next instruction
- if srcstep == vl or dststep == vl:
+ pre = yield from self.update_new_svstate_steps()
+ if pre:
self.svp64_reset_loop()
+ self.update_nia()
self.update_pc_next()
return
+ srcstep, dststep = self.get_src_dststeps()
+ pred_dst_zero = self.pred_dst_zero
+ pred_src_zero = self.pred_src_zero
+ vl = self.svstate.vl
# VL=0 in SVP64 mode means "do nothing: skip instruction"
if self.is_svp64_mode and vl == 0:
self.pc.update(self.namespace, self.is_svp64_mode)
- print("SVP64: VL=0, end of call", self.namespace['CIA'],
+ log("SVP64: VL=0, end of call", self.namespace['CIA'],
self.namespace['NIA'])
return
+ # for when SVREMAP is active, using pre-arranged schedule.
+ # note: modifying PowerDecoder2 needs to "settle"
+ remap_en = self.svstate.SVme
+ persist = self.svstate.RMpst
+ active = (persist or self.last_op_svshape) and remap_en != 0
+ yield self.dec2.remap_active.eq(remap_en if active else 0)
+ yield Settle()
+ if persist or self.last_op_svshape:
+ remaps = self.get_remap_indices()
+ if self.is_svp64_mode and (persist or self.last_op_svshape):
+ # just some convenient debug info
+ for i in range(4):
+ sname = 'SVSHAPE%d' % i
+ shape = self.spr[sname]
+ log (sname, bin(shape.value))
+ log (" lims", shape.lims)
+ log (" mode", shape.mode)
+ log (" skip", shape.skip)
+
+ # set up the list of steps to remap
+ mi0 = self.svstate.mi0
+ mi1 = self.svstate.mi1
+ mi2 = self.svstate.mi2
+ mo0 = self.svstate.mo0
+ mo1 = self.svstate.mo1
+ steps = [(self.dec2.in1_step, mi0), # RA
+ (self.dec2.in2_step, mi1), # RB
+ (self.dec2.in3_step, mi2), # RC
+ (self.dec2.o_step, mo0), # RT
+ (self.dec2.o2_step, mo1), # EA
+ ]
+ remap_idxs = self.remap_idxs
+ rremaps = []
+ # now cross-index the required SHAPE for each of 3-in 2-out regs
+ rnames = ['RA', 'RB', 'RC', 'RT', 'EA']
+ for i, (dstep, shape_idx) in enumerate(steps):
+ (shape, remap) = remaps[shape_idx]
+ remap_idx = remap_idxs[shape_idx]
+ # zero is "disabled"
+ if shape.value == 0x0:
+ continue
+ # now set the actual requested step to the current index
+ yield dstep.eq(remap_idx)
+
+ # debug printout info
+ rremaps.append((shape.mode, i, rnames[i], shape_idx,
+ remap_idx))
+ for x in rremaps:
+ log ("shape remap", x)
+ # after that, settle down (combinatorial) to let Vector reg numbers
+ # work themselves out
+ yield Settle()
+ remap_active = yield self.dec2.remap_active
+ log ("remap active", bin(remap_active))
+
# main input registers (RT, RA ...)
inputs = []
for name in input_names:
# doing this is not part of svp64, it's because output
# registers, to be modified, need to be in the namespace.
regnum, is_vec = yield from get_pdecode_idx_out(self.dec2, name)
+ if regnum is None:
+ regnum, is_vec = yield from get_pdecode_idx_out2(self.dec2,
+ name)
# in case getting the register number is needed, _RA, _RB
regname = "_" + name
self.namespace[regname] = regnum
if not self.is_svp64_mode or not pred_src_zero:
- print('reading reg %s %s' % (name, str(regnum)), is_vec)
+ log('reading reg %s %s' % (name, str(regnum)), is_vec)
if name in fregs:
- reg_val = self.fpr(regnum)
- else:
- reg_val = self.gpr(regnum)
+ reg_val = SelectableInt(self.fpr(regnum))
+ elif name is not None:
+ reg_val = SelectableInt(self.gpr(regnum))
else:
- print('zero input reg %s %s' % (name, str(regnum)), is_vec)
+ log('zero input reg %s %s' % (name, str(regnum)), is_vec)
reg_val = 0
inputs.append(reg_val)
+ # arrrrgh, awful hack, to get _RT into namespace
+ if ins_name in ['setvl', 'svstep']:
+ regname = "_RT"
+ RT = yield self.dec2.dec.RT
+ self.namespace[regname] = SelectableInt(RT, 5)
+ if RT == 0:
+ self.namespace["RT"] = SelectableInt(0, 5)
+ regnum, is_vec = yield from get_pdecode_idx_out(self.dec2, "RT")
+ log('hack input reg %s %s' % (name, str(regnum)), is_vec)
+
+ # in SVP64 mode for LD/ST work out immediate
+ # XXX TODO: replace_ds for DS-Form rather than D-Form.
+ # use info.form to detect
+ replace_d = False # update / replace constant in pseudocode
+ if self.is_svp64_mode:
+ ldstmode = yield self.dec2.rm_dec.ldstmode
+ # shift mode reads SVD (or SVDS - TODO)
+ # *BUT*... because this is "overloading" of LD operations,
+ # it gets *STORED* into D (or DS, TODO)
+ if ldstmode == SVP64LDSTmode.SHIFT.value:
+ imm = yield self.dec2.dec.fields.FormSVD.SVD[0:11]
+ imm = exts(imm, 11) # sign-extend to integer
+ log ("shift SVD", imm)
+ replace_d = True
+ else:
+ if info.form == 'DS':
+ # DS-Form, multiply by 4 then knock 2 bits off after
+ imm = yield self.dec2.dec.fields.FormDS.DS[0:14] * 4
+ else:
+ imm = yield self.dec2.dec.fields.FormD.D[0:16]
+ imm = exts(imm, 16) # sign-extend to integer
+ # get the right step. LD is from srcstep, ST is dststep
+ op = yield self.dec2.e.do.insn_type
+ offsmul = 0
+ if op == MicrOp.OP_LOAD.value:
+ if remap_active:
+ offsmul = yield self.dec2.in1_step
+ log("D-field REMAP src", imm, offsmul)
+ else:
+ offsmul = srcstep
+ log("D-field src", imm, offsmul)
+ elif op == MicrOp.OP_STORE.value:
+ # XXX NOTE! no bit-reversed STORE! this should not ever be used
+ offsmul = dststep
+ log("D-field dst", imm, offsmul)
+ # bit-reverse mode, rev already done through get_src_dst_steps()
+ if ldstmode == SVP64LDSTmode.SHIFT.value:
+ # manually look up RC, sigh
+ RC = yield self.dec2.dec.RC[0:5]
+ RC = self.gpr(RC)
+ log ("LD-SHIFT:", "VL", vl,
+ "RC", RC.value, "imm", imm,
+ "offs", bin(offsmul),
+ )
+ imm = SelectableInt((imm * offsmul) << RC.value, 32)
+ # Unit-Strided LD/ST adds offset*width to immediate
+ elif ldstmode == SVP64LDSTmode.UNITSTRIDE.value:
+ ldst_len = yield self.dec2.e.do.data_len
+ imm = SelectableInt(imm + offsmul * ldst_len, 32)
+ replace_d = True
+ # Element-strided multiplies the immediate by element step
+ elif ldstmode == SVP64LDSTmode.ELSTRIDE.value:
+ imm = SelectableInt(imm * offsmul, 32)
+ replace_d = True
+ if replace_d:
+ ldst_ra_vec = yield self.dec2.rm_dec.ldst_ra_vec
+ ldst_imz_in = yield self.dec2.rm_dec.ldst_imz_in
+ log("LDSTmode", SVP64LDSTmode(ldstmode),
+ offsmul, imm, ldst_ra_vec, ldst_imz_in)
+ # new replacement D... errr.. DS
+ if replace_d:
+ if info.form == 'DS':
+ # TODO: assert 2 LSBs are zero?
+ log("DS-Form, TODO, assert 2 LSBs zero?", bin(imm.value))
+ imm.value = imm.value >> 2
+ self.namespace['DS'] = imm
+ else:
+ self.namespace['D'] = imm
# "special" registers
for special in info.special_regs:
# clear trap (trap) NIA
self.trap_nia = None
- # execute actual instruction here
- print("inputs", inputs)
+ # check if this was an sv.bc* and create an indicator that
+ # this is the last check to be made as a loop. combined with
+ # the ALL/ANY mode we can early-exit
+ if self.is_svp64_mode and ins_name.startswith("sv.bc"):
+ no_in_vec = yield self.dec2.no_in_vec # BI is scalar
+ end_loop = no_in_vec or srcstep == vl-1 or dststep == vl-1
+ self.namespace['end_loop'] = SelectableInt(end_loop, 1)
+
+ # execute actual instruction here (finally)
+ log("inputs", inputs)
results = info.func(self, *inputs)
- print("results", results)
+ log("results", results)
# "inject" decorator takes namespace from function locals: we need to
# overwrite NIA being overwritten (sigh)
if self.trap_nia is not None:
self.namespace['NIA'] = self.trap_nia
- print("after func", self.namespace['CIA'], self.namespace['NIA'])
+ log("after func", self.namespace['CIA'], self.namespace['NIA'])
+
+ # check if op was a LD/ST so that debugging can check the
+ # address
+ if int_op in [MicrOp.OP_STORE.value,
+ ]:
+ self.last_st_addr = self.mem.last_st_addr
+ if int_op in [MicrOp.OP_LOAD.value,
+ ]:
+ self.last_ld_addr = self.mem.last_ld_addr
+ log ("op", int_op, MicrOp.OP_STORE.value, MicrOp.OP_LOAD.value,
+ self.last_st_addr, self.last_ld_addr)
# detect if CA/CA32 already in outputs (sra*, basically)
already_done = 0
if name == 'CA32':
already_done |= 2
- print("carry already done?", bin(already_done))
+ log("carry already done?", bin(already_done))
if hasattr(self.dec2.e.do, "output_carry"):
carry_en = yield self.dec2.e.do.output_carry
else:
else:
ov_en = False
ov_ok = False
- print("internal overflow", overflow, ov_en, ov_ok)
+ log("internal overflow", overflow, ov_en, ov_ok)
if ov_en & ov_ok:
yield from self.handle_overflow(inputs, results, overflow)
if not self.is_svp64_mode or not pred_dst_zero:
if hasattr(self.dec2.e.do, "rc"):
rc_en = yield self.dec2.e.do.rc.rc
- if rc_en:
+ if rc_en and ins_name not in ['svstep']:
regnum, is_vec = yield from get_pdecode_cr_out(self.dec2, "CR0")
self.handle_comparison(results, regnum)
output = SelectableInt(output, 256)
if name in ['CA', 'CA32']:
if carry_en:
- print("writing %s to XER" % name, output)
+ log("writing %s to XER" % name, output)
self.spr['XER'][XER_bits[name]] = output.value
else:
- print("NOT writing %s to XER" % name, output)
+ log("NOT writing %s to XER" % name, output)
elif name in info.special_regs:
- print('writing special %s' % name, output, special_sprs)
+ log('writing special %s' % name, output, special_sprs)
if name in special_sprs:
self.spr[name] = output
else:
self.namespace[name].eq(output)
if name == 'MSR':
- print('msr written', hex(self.msr.value))
+ log('msr written', hex(self.msr.value))
else:
regnum, is_vec = yield from get_pdecode_idx_out(self.dec2,
name)
+ if regnum is None:
+ regnum, is_vec = yield from get_pdecode_idx_out2(
+ self.dec2, name)
if regnum is None:
# temporary hack for not having 2nd output
regnum = yield getattr(self.decoder, name)
is_vec = False
if self.is_svp64_mode and pred_dst_zero:
- print('zeroing reg %d %s' % (regnum, str(output)),
+ log('zeroing reg %d %s' % (regnum, str(output)),
is_vec)
output = SelectableInt(0, 256)
else:
ftype = 'fpr'
else:
ftype = 'gpr'
- print('writing %s %s %s' % (regnum, ftype, str(output)),
+ log('writing %s %s %s' % (ftype, regnum, str(output)),
is_vec)
if output.bits > 64:
output = SelectableInt(output.value, 64)
# check if it is the SVSTATE.src/dest step that needs incrementing
# this is our Sub-Program-Counter loop from 0 to VL-1
- if self.is_svp64_mode:
- # XXX twin predication TODO
- vl = self.svstate.vl.asint(msb0=True)
- mvl = self.svstate.maxvl.asint(msb0=True)
- srcstep = self.svstate.srcstep.asint(msb0=True)
- dststep = self.svstate.dststep.asint(msb0=True)
- sv_ptype = yield self.dec2.dec.op.SV_Ptype
- no_out_vec = not (yield self.dec2.no_out_vec)
- no_in_vec = not (yield self.dec2.no_in_vec)
- print (" svstate.vl", vl)
- print (" svstate.mvl", mvl)
- print (" svstate.srcstep", srcstep)
- print (" svstate.dststep", dststep)
- print (" no_out_vec", no_out_vec)
- print (" no_in_vec", no_in_vec)
- print (" sv_ptype", sv_ptype, sv_ptype == SVPtype.P2.value)
- # check if srcstep needs incrementing by one, stop PC advancing
- # svp64 loop can end early if the dest is scalar for single-pred
- # but for 2-pred both src/dest have to be checked.
- # XXX this might not be true! it may just be LD/ST
- if sv_ptype == SVPtype.P2.value:
- svp64_is_vector = (no_out_vec or no_in_vec)
+ pre = False
+ post = False
+ nia_update = True
+ if self.allow_next_step_inc:
+ log("SVSTATE_NEXT: inc requested, mode",
+ self.svstate_next_mode, self.allow_next_step_inc)
+ yield from self.svstate_pre_inc()
+ pre = yield from self.update_new_svstate_steps()
+ if pre:
+ # reset at end of loop including exit Vertical Mode
+ log ("SVSTATE_NEXT: end of loop, reset")
+ self.svp64_reset_loop()
+ self.svstate.vfirst = 0
+ self.update_nia()
+ if rc_en:
+ results = [SelectableInt(0, 64)]
+ self.handle_comparison(results) # CR0
else:
- svp64_is_vector = no_out_vec
- if svp64_is_vector and srcstep != vl-1 and dststep != vl-1:
- self.svstate.srcstep += SelectableInt(1, 7)
- self.svstate.dststep += SelectableInt(1, 7)
- self.pc.NIA.value = self.pc.CIA.value
- self.namespace['NIA'] = self.pc.NIA
+ if self.allow_next_step_inc == 2:
+ log ("SVSTATE_NEXT: read")
+ nia_update = (yield from self.svstate_post_inc(ins_name))
+ else:
+ log ("SVSTATE_NEXT: post-inc")
+ # use actual src/dst-step here to check end, do NOT
+ # use bit-reversed version
+ srcstep, dststep = self.new_srcstep, self.new_dststep
+ remaps = self.get_remap_indices()
+ remap_idxs = self.remap_idxs
+ vl = self.svstate.vl
+ end_src = srcstep == vl-1
+ end_dst = dststep == vl-1
+ if self.allow_next_step_inc != 2:
+ if not end_src:
+ self.svstate.srcstep += SelectableInt(1, 7)
+ if not end_dst:
+ self.svstate.dststep += SelectableInt(1, 7)
self.namespace['SVSTATE'] = self.svstate.spr
- print("end of sub-pc call", self.namespace['CIA'],
- self.namespace['NIA'])
- return # DO NOT allow PC to update whilst Sub-PC loop running
- # reset loop to zero
- self.svp64_reset_loop()
+ # set CR0 (if Rc=1) based on end
+ if rc_en:
+ srcstep = self.svstate.srcstep
+ dststep = self.svstate.srcstep
+ endtest = 1 if (end_src or end_dst) else 0
+ #results = [SelectableInt(endtest, 64)]
+ #self.handle_comparison(results) # CR0
+
+ # see if svstep was requested, if so, which SVSTATE
+ endings = 0b111
+ if self.svstate_next_mode > 0:
+ shape_idx = self.svstate_next_mode.value-1
+ endings = self.remap_loopends[shape_idx]
+ cr_field = SelectableInt((~endings)<<1 | endtest, 4)
+ print ("svstep Rc=1, CR0", cr_field)
+ self.crl[0].eq(cr_field) # CR0
+ if end_src or end_dst:
+ # reset at end of loop including exit Vertical Mode
+ log ("SVSTATE_NEXT: after increments, reset")
+ self.svp64_reset_loop()
+ self.svstate.vfirst = 0
+
+ elif self.is_svp64_mode:
+ nia_update = (yield from self.svstate_post_inc(ins_name))
+ else:
+ # XXX only in non-SVP64 mode!
+ # record state of whether the current operation was an svshape,
+ # to be able to know if it should apply in the next instruction.
+ # also (if going to use this instruction) should disable ability
+ # to interrupt in between. sigh.
+ self.last_op_svshape = asmop == 'svremap'
+
+ if nia_update:
+ self.update_pc_next()
+
+ def SVSTATE_NEXT(self, mode, submode):
+ """explicitly moves srcstep/dststep on to next element, for
+ "Vertical-First" mode. this function is called from
+ setvl pseudo-code, as a pseudo-op "svstep"
+
+ WARNING: this function uses information that was created EARLIER
+ due to it being in the middle of a yield, but this function is
+ *NOT* called from yield (it's called from compiled pseudocode).
+ """
+ self.allow_next_step_inc = submode.value + 1
+ log("SVSTATE_NEXT mode", mode, submode, self.allow_next_step_inc)
+ self.svstate_next_mode = mode
+ if self.svstate_next_mode > 0:
+ shape_idx = self.svstate_next_mode.value-1
+ return SelectableInt(self.remap_idxs[shape_idx], 7)
+ return SelectableInt(0, 7)
+
+ def svstate_pre_inc(self):
+ """check if srcstep/dststep need to skip over masked-out predicate bits
+ """
+ # get SVSTATE VL (oh and print out some debug stuff)
+ vl = self.svstate.vl
+ srcstep = self.svstate.srcstep
+ dststep = self.svstate.dststep
+ sv_a_nz = yield self.dec2.sv_a_nz
+ fft_mode = yield self.dec2.use_svp64_fft
+ in1 = yield self.dec2.e.read_reg1.data
+ log ("SVP64: VL, srcstep, dststep, sv_a_nz, in1 fft, svp64",
+ vl, srcstep, dststep, sv_a_nz, in1, fft_mode,
+ self.is_svp64_mode)
- self.update_pc_next()
+ # get predicate mask
+ srcmask = dstmask = 0xffff_ffff_ffff_ffff
+
+ pmode = yield self.dec2.rm_dec.predmode
+ reverse_gear = yield self.dec2.rm_dec.reverse_gear
+ sv_ptype = yield self.dec2.dec.op.SV_Ptype
+ srcpred = yield self.dec2.rm_dec.srcpred
+ dstpred = yield self.dec2.rm_dec.dstpred
+ pred_src_zero = yield self.dec2.rm_dec.pred_sz
+ pred_dst_zero = yield self.dec2.rm_dec.pred_dz
+ if pmode == SVP64PredMode.INT.value:
+ srcmask = dstmask = get_predint(self.gpr, dstpred)
+ if sv_ptype == SVPtype.P2.value:
+ srcmask = get_predint(self.gpr, srcpred)
+ elif pmode == SVP64PredMode.CR.value:
+ srcmask = dstmask = get_predcr(self.crl, dstpred, vl)
+ if sv_ptype == SVPtype.P2.value:
+ srcmask = get_predcr(self.crl, srcpred, vl)
+ log (" pmode", pmode)
+ log (" reverse", reverse_gear)
+ log (" ptype", sv_ptype)
+ log (" srcpred", bin(srcpred))
+ log (" dstpred", bin(dstpred))
+ log (" srcmask", bin(srcmask))
+ log (" dstmask", bin(dstmask))
+ log (" pred_sz", bin(pred_src_zero))
+ log (" pred_dz", bin(pred_dst_zero))
+
+ # okaaay, so here we simply advance srcstep (TODO dststep)
+ # until the predicate mask has a "1" bit... or we run out of VL
+ # let srcstep==VL be the indicator to move to next instruction
+ if not pred_src_zero:
+ while (((1<<srcstep) & srcmask) == 0) and (srcstep != vl):
+ log (" skip", bin(1<<srcstep))
+ srcstep += 1
+ # same for dststep
+ if not pred_dst_zero:
+ while (((1<<dststep) & dstmask) == 0) and (dststep != vl):
+ log (" skip", bin(1<<dststep))
+ dststep += 1
+
+ # now work out if the relevant mask bits require zeroing
+ if pred_dst_zero:
+ pred_dst_zero = ((1<<dststep) & dstmask) == 0
+ if pred_src_zero:
+ pred_src_zero = ((1<<srcstep) & srcmask) == 0
+
+ # store new srcstep / dststep
+ self.new_srcstep, self.new_dststep = srcstep, dststep
+ self.pred_dst_zero, self.pred_src_zero = pred_dst_zero, pred_src_zero
+ log (" new srcstep", srcstep)
+ log (" new dststep", dststep)
+
+ def get_src_dststeps(self):
+ """gets srcstep and dststep
+ """
+ return self.new_srcstep, self.new_dststep
+
+ def update_new_svstate_steps(self):
+ # note, do not get the bit-reversed srcstep here!
+ srcstep, dststep = self.new_srcstep, self.new_dststep
+
+ # update SVSTATE with new srcstep
+ self.svstate.srcstep = srcstep
+ self.svstate.dststep = dststep
+ self.namespace['SVSTATE'] = self.svstate
+ yield self.dec2.state.svstate.eq(self.svstate.value)
+ yield Settle() # let decoder update
+ srcstep = self.svstate.srcstep
+ dststep = self.svstate.dststep
+ vl = self.svstate.vl
+ log (" srcstep", srcstep)
+ log (" dststep", dststep)
+ log (" vl", vl)
+
+ # check if end reached (we let srcstep overrun, above)
+ # nothing needs doing (TODO zeroing): just do next instruction
+ return srcstep == vl or dststep == vl
+
+ def svstate_post_inc(self, insn_name, vf=0):
+ # check if SV "Vertical First" mode is enabled
+ vfirst = self.svstate.vfirst
+ log (" SV Vertical First", vf, vfirst)
+ if not vf and vfirst == 1:
+ self.update_nia()
+ return True
+
+ # check if it is the SVSTATE.src/dest step that needs incrementing
+ # this is our Sub-Program-Counter loop from 0 to VL-1
+ # XXX twin predication TODO
+ vl = self.svstate.vl
+ mvl = self.svstate.maxvl
+ srcstep = self.svstate.srcstep
+ dststep = self.svstate.dststep
+ rm_mode = yield self.dec2.rm_dec.mode
+ reverse_gear = yield self.dec2.rm_dec.reverse_gear
+ sv_ptype = yield self.dec2.dec.op.SV_Ptype
+ out_vec = not (yield self.dec2.no_out_vec)
+ in_vec = not (yield self.dec2.no_in_vec)
+ log (" svstate.vl", vl)
+ log (" svstate.mvl", mvl)
+ log (" svstate.srcstep", srcstep)
+ log (" svstate.dststep", dststep)
+ log (" mode", rm_mode)
+ log (" reverse", reverse_gear)
+ log (" out_vec", out_vec)
+ log (" in_vec", in_vec)
+ log (" sv_ptype", sv_ptype, sv_ptype == SVPtype.P2.value)
+ # check if srcstep needs incrementing by one, stop PC advancing
+ # svp64 loop can end early if the dest is scalar for single-pred
+ # but for 2-pred both src/dest have to be checked.
+ # XXX this might not be true! it may just be LD/ST
+ if sv_ptype == SVPtype.P2.value:
+ svp64_is_vector = (out_vec or in_vec)
+ else:
+ svp64_is_vector = out_vec
+ # check if this was an sv.bc* and if so did it succeed
+ if self.is_svp64_mode and insn_name.startswith("sv.bc"):
+ end_loop = self.namespace['end_loop']
+ log("branch %s end_loop" % insn_name, end_loop)
+ if end_loop.value:
+ self.svp64_reset_loop()
+ self.update_pc_next()
+ return False
+ if svp64_is_vector and srcstep != vl-1 and dststep != vl-1:
+ self.svstate.srcstep += SelectableInt(1, 7)
+ self.svstate.dststep += SelectableInt(1, 7)
+ self.namespace['SVSTATE'] = self.svstate
+ # not an SVP64 branch, so fix PC (NIA==CIA) for next loop
+ # (by default, NIA is CIA+4 if v3.0B or CIA+8 if SVP64)
+ # this way we keep repeating the same instruction (with new steps)
+ self.pc.NIA.value = self.pc.CIA.value
+ self.namespace['NIA'] = self.pc.NIA
+ log("end of sub-pc call", self.namespace['CIA'],
+ self.namespace['NIA'])
+ return False # DO NOT allow PC update whilst Sub-PC loop running
+
+ # reset loop to zero and update NIA
+ self.svp64_reset_loop()
+ self.update_nia()
+
+ return True
def update_pc_next(self):
# UPDATE program counter
self.pc.update(self.namespace, self.is_svp64_mode)
self.svstate.spr = self.namespace['SVSTATE']
- print("end of call", self.namespace['CIA'],
+ log("end of call", self.namespace['CIA'],
self.namespace['NIA'],
self.namespace['SVSTATE'])
def svp64_reset_loop(self):
- self.svstate.srcstep[0:7] = 0
- self.svstate.dststep[0:7] = 0
- print (" svstate.srcstep loop end (PC to update)")
+ self.svstate.srcstep = 0
+ self.svstate.dststep = 0
+ log (" svstate.srcstep loop end (PC to update)")
+ self.namespace['SVSTATE'] = self.svstate
+
+ def update_nia(self):
self.pc.update_nia(self.is_svp64_mode)
self.namespace['NIA'] = self.pc.NIA
- self.namespace['SVSTATE'] = self.svstate.spr
+
def inject():
"""Decorator factory.
context = args[0].namespace # variables to be injected
saved_values = func_globals.copy() # Shallow copy of dict.
+ log("globals before", context.keys())
func_globals.update(context)
result = func(*args, **kwargs)
- print("globals after", func_globals['CIA'], func_globals['NIA'])
- print("args[0]", args[0].namespace['CIA'],
+ log("globals after", func_globals['CIA'], func_globals['NIA'])
+ log("args[0]", args[0].namespace['CIA'],
args[0].namespace['NIA'],
args[0].namespace['SVSTATE'])
+ if 'end_loop' in func_globals:
+ log("args[0] end_loop", func_globals['end_loop'])
args[0].namespace = func_globals
#exec (func.__code__, func_globals)
projects / openpower-isa.git / blobdiff