selectconcat)
from openpower.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
insns, MicrOp, In1Sel, In2Sel, In3Sel,
- OutSel, CROutSel, LDSTMode,
+ OutSel, CRInSel, CROutSel, LDSTMode,
SVP64RMMode, SVP64PredMode,
SVP64PredInt, SVP64PredCR,
SVP64LDSTmode)
from openpower.decoder.power_enums import SVPtype
-from openpower.decoder.helpers import (exts, gtu, ltu, undefined, bitrev)
+from openpower.decoder.helpers import (exts, gtu, ltu, undefined,
+ ISACallerHelper, ISAFPHelpers)
from openpower.consts import PIb, MSRb # big-endian (PowerISA versions)
-from openpower.consts import SVP64CROffs
+from openpower.consts import (SVP64MODE,
+ SVP64CROffs,
+ )
from openpower.decoder.power_svp64 import SVP64RM, decode_extra
from openpower.decoder.isa.radixmmu import RADIX
"RB": 0,
"RC": 0,
"RS": 0,
+ "BI": 0,
"CR": 0,
"LR": 0,
"CTR": 0,
return None, False
+# TODO, really should just be using PowerDecoder2
+def get_pdecode_cr_in(dec2, name):
+ op = dec2.dec.op
+ in_sel = yield op.cr_in
+ in_bitfield = yield dec2.dec_cr_in.cr_bitfield.data
+ sv_cr_in = yield op.sv_cr_in
+ spec = yield dec2.crin_svdec.spec
+ sv_override = yield dec2.dec_cr_in.sv_override
+ # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
+ in1 = yield dec2.e.read_cr1.data
+ cr_isvec = yield dec2.cr_in_isvec
+ log ("get_pdecode_cr_in", in_sel, CROutSel.CR0.value, in1, cr_isvec)
+ log (" sv_cr_in", sv_cr_in)
+ log (" cr_bf", in_bitfield)
+ log (" spec", spec)
+ log (" override", sv_override)
+ # identify which regnames map to in / o2
+ if name == 'BI':
+ if in_sel == CRInSel.BI.value:
+ return in1, cr_isvec
+ log ("get_pdecode_cr_in not found", name)
+ return None, False
+
+
# TODO, really should just be using PowerDecoder2
def get_pdecode_cr_out(dec2, name):
op = dec2.dec.op
dec2.dec.RT)
if out_sel == OutSel.RT.value:
return out, o_isvec
+ elif name == 'RT_OR_ZERO':
+ log ("get_pdecode_idx_out", out_sel, OutSel.RT.value,
+ OutSel.RT_OR_ZERO.value, out, o_isvec,
+ dec2.dec.RT)
+ if out_sel == OutSel.RT_OR_ZERO.value:
+ return out, o_isvec
elif name == 'FRA':
log ("get_pdecode_idx_out", out_sel, OutSel.FRA.value, out, o_isvec)
if out_sel == OutSel.FRA.value:
return None, False
-class ISACaller:
+class ISACaller(ISACallerHelper, ISAFPHelpers):
# decoder2 - an instance of power_decoder2
# regfile - a list of initial values for the registers
# initial_{etc} - initial values for SPRs, Condition Register, Mem, MSR
self.msr = SelectableInt(initial_msr, 64) # underlying reg
self.pc = PC()
# GPR FPR SPR registers
+ initial_sprs = copy(initial_sprs) # so as not to get modified
self.gpr = GPR(decoder2, self, self.svstate, regfile)
self.fpr = GPR(decoder2, self, self.svstate, fpregfile)
self.spr = SPR(decoder2, initial_sprs) # initialise SPRs before MMU
'MSR': self.msr,
'undefined': undefined,
'mode_is_64bit': True,
- 'SO': XER_bits['SO']
+ 'SO': XER_bits['SO'],
+ 'XLEN': 64 # elwidth overrides, later
})
# update pc to requested start point
def memassign(self, ea, sz, val):
self.mem.memassign(ea, sz, val)
- def prep_namespace(self, formname, op_fields):
+ def prep_namespace(self, insn_name, formname, op_fields):
# TODO: get field names from form in decoder*1* (not decoder2)
# decoder2 is hand-created, and decoder1.sigform is auto-generated
# from spec
fields = self.decoder.sigforms[formname]
log("prep_namespace", formname, op_fields)
for name in op_fields:
- if name == 'spr':
- sig = getattr(fields, name.upper())
- else:
+ # CR immediates. deal with separately. needs modifying
+ # pseudocode
+ if self.is_svp64_mode and name in ['BI']: # TODO, more CRs
+ # BI is a 5-bit, must reconstruct the value
+ regnum, is_vec = yield from get_pdecode_cr_in(self.dec2, name)
sig = getattr(fields, name)
- val = yield sig
+ val = yield sig
+ # low 2 LSBs (CR field selector) remain same, CR num extended
+ assert regnum <= 7, "sigh, TODO, 128 CR fields"
+ val = (val & 0b11) | (regnum<<2)
+ else:
+ if name == 'spr':
+ sig = getattr(fields, name.upper())
+ else:
+ sig = getattr(fields, name)
+ val = yield sig
# these are all opcode fields involved in index-selection of CR,
# and need to do "standard" arithmetic. CR[BA+32] for example
# would, if using SelectableInt, only be 5-bit.
self.namespace['VL'] = vl
self.namespace['srcstep'] = srcstep
+ # sv.bc* need some extra fields
+ if self.is_svp64_mode and insn_name.startswith("sv.bc"):
+ # blegh grab bits manually
+ mode = yield self.dec2.rm_dec.rm_in.mode
+ bc_vlset = (mode & SVP64MODE.BC_VLSET) != 0
+ bc_vli = (mode & SVP64MODE.BC_VLI) != 0
+ bc_snz = (mode & SVP64MODE.BC_SNZ) != 0
+ bc_vsb = yield self.dec2.rm_dec.bc_vsb
+ bc_lru = yield self.dec2.rm_dec.bc_lru
+ bc_gate = yield self.dec2.rm_dec.bc_gate
+ sz = yield self.dec2.rm_dec.pred_sz
+ self.namespace['ALL'] = SelectableInt(bc_gate, 1)
+ self.namespace['VSb'] = SelectableInt(bc_vsb, 1)
+ self.namespace['LRu'] = SelectableInt(bc_lru, 1)
+ self.namespace['VLSET'] = SelectableInt(bc_vlset, 1)
+ self.namespace['VLI'] = SelectableInt(bc_vli, 1)
+ self.namespace['sz'] = SelectableInt(sz, 1)
+ self.namespace['SNZ'] = SelectableInt(bc_snz, 1)
+
def handle_carry_(self, inputs, outputs, already_done):
inv_a = yield self.dec2.e.do.invert_in
if inv_a:
SO = self.spr['XER'][XER_bits['SO']]
log("handle_comparison SO", SO)
cr_field = selectconcat(negative, positive, zero, SO)
+ log("handle_comparison cr_field", self.cr, cr_idx, cr_field)
self.crl[cr_idx].eq(cr_field)
def set_pc(self, pc_val):
if not self.respect_pc:
self.fake_pc += 4
- log("execute one, CIA NIA", self.pc.CIA.value, self.pc.NIA.value)
+ log("execute one, CIA NIA", hex(self.pc.CIA.value),
+ hex(self.pc.NIA.value))
def get_assembly_name(self):
# TODO, asmregs is from the spec, e.g. add RT,RA,RB
asmop = 'mtcrf'
return asmop
+ def get_remap_indices(self):
+ """WARNING, this function stores remap_idxs and remap_loopends
+ in the class for later use. this to avoid problems with yield
+ """
+ # go through all iterators in lock-step, advance to next remap_idx
+ srcstep, dststep = self.get_src_dststeps()
+ # get four SVSHAPEs. here we are hard-coding
+ SVSHAPE0 = self.spr['SVSHAPE0']
+ SVSHAPE1 = self.spr['SVSHAPE1']
+ SVSHAPE2 = self.spr['SVSHAPE2']
+ SVSHAPE3 = self.spr['SVSHAPE3']
+ # set up the iterators
+ remaps = [(SVSHAPE0, SVSHAPE0.get_iterator()),
+ (SVSHAPE1, SVSHAPE1.get_iterator()),
+ (SVSHAPE2, SVSHAPE2.get_iterator()),
+ (SVSHAPE3, SVSHAPE3.get_iterator()),
+ ]
+
+ self.remap_loopends = [0] * 4
+ self.remap_idxs = [0, 1, 2, 3]
+ dbg = []
+ for i, (shape, remap) in enumerate(remaps):
+ # zero is "disabled"
+ if shape.value == 0x0:
+ self.remap_idxs[i] = 0
+ # pick src or dststep depending on reg num (0-2=in, 3-4=out)
+ step = dststep if (i in [3, 4]) else srcstep
+ # this is terrible. O(N^2) looking for the match. but hey.
+ for idx, (remap_idx, loopends) in enumerate(remap):
+ if idx == step:
+ break
+ self.remap_idxs[i] = remap_idx
+ self.remap_loopends[i] = loopends
+ dbg.append((i, step, remap_idx, loopends))
+ for (i, step, remap_idx, loopends) in dbg:
+ log ("SVSHAPE %d idx, end" % i, step, remap_idx, bin(loopends))
+ return remaps
+
def get_spr_msb(self):
dec_insn = yield self.dec2.e.do.insn
return dec_insn & (1 << 20) != 0 # sigh - XFF.spr[-1]?
self.last_st_addr = None # reset the last known store address
self.last_ld_addr = None # etc.
- name = name.strip() # remove spaces if not already done so
+ ins_name = name.strip() # remove spaces if not already done so
if self.halted:
- log("halted - not executing", name)
+ log("halted - not executing", ins_name)
return
# TODO, asmregs is from the spec, e.g. add RT,RA,RB
# see http://bugs.libre-riscv.org/show_bug.cgi?id=282
asmop = yield from self.get_assembly_name()
- log("call", name, asmop)
+ log("call", ins_name, asmop)
# check privileged
int_op = yield self.dec2.dec.op.internal_op
return
# check halted condition
- if name == 'attn':
+ if ins_name == 'attn':
self.halted = True
return
# check illegal instruction
illegal = False
- if name not in ['mtcrf', 'mtocrf']:
- illegal = name != asmop
+ if ins_name not in ['mtcrf', 'mtocrf']:
+ illegal = ins_name != asmop
# sigh deal with setvl not being supported by binutils (.long)
if asmop.startswith('setvl'):
illegal = False
- name = 'setvl'
+ ins_name = 'setvl'
+
+ # and svstep not being supported by binutils (.long)
+ if asmop.startswith('svstep'):
+ illegal = False
+ ins_name = 'svstep'
# and svremap not being supported by binutils (.long)
if asmop.startswith('svremap'):
illegal = False
- name = 'svremap'
+ ins_name = 'svremap'
# and svshape not being supported by binutils (.long)
if asmop.startswith('svshape'):
illegal = False
- name = 'svshape'
+ ins_name = 'svshape'
+
+ # and fsin and fcos
+ if asmop == 'fsins':
+ illegal = False
+ ins_name = 'fsins'
+ if asmop == 'fcoss':
+ illegal = False
+ ins_name = 'fcoss'
# sigh also deal with ffmadds not being supported by binutils (.long)
if asmop == 'ffmadds':
illegal = False
- name = 'ffmadds'
+ ins_name = 'ffmadds'
+
+ # and fdmadds not being supported by binutils (.long)
+ if asmop == 'fdmadds':
+ illegal = False
+ ins_name = 'fdmadds'
# and ffadds not being supported by binutils (.long)
if asmop == 'ffadds':
illegal = False
- name = 'ffadds'
+ ins_name = 'ffadds'
+
+ # branch-conditional redirects to sv.bc
+ if asmop.startswith('bc') and self.is_svp64_mode:
+ ins_name = 'sv.%s' % ins_name
+
+ log(" post-processed name", ins_name, asmop)
+ # illegal instructions call TRAP at 0x700
if illegal:
- print("illegal", name, asmop)
+ print("illegal", ins_name, asmop)
self.call_trap(0x700, PIb.ILLEG)
print("name %s != %s - calling ILLEGAL trap, PC: %x" %
- (name, asmop, self.pc.CIA.value))
+ (ins_name, asmop, self.pc.CIA.value))
return
# this is for setvl "Vertical" mode: if set true,
- # srcstep/dststep is explicitly advanced
+ # srcstep/dststep is explicitly advanced. mode says which SVSTATE to
+ # test for Rc=1 end condition. 3 bits of all 3 loops are put into CR0
self.allow_next_step_inc = False
+ self.svstate_next_mode = 0
# nop has to be supported, we could let the actual op calculate
# but PowerDecoder has a pattern for nop
- if name is 'nop':
+ if ins_name is 'nop':
self.update_pc_next()
return
- info = self.instrs[name]
- yield from self.prep_namespace(info.form, info.op_fields)
+ # look up instruction in ISA.instrs, prepare namespace
+ info = self.instrs[ins_name]
+ yield from self.prep_namespace(ins_name, info.form, info.op_fields)
# preserve order of register names
input_names = create_args(list(info.read_regs) +
log("input names", input_names)
# get SVP64 entry for the current instruction
- sv_rm = self.svp64rm.instrs.get(name)
+ sv_rm = self.svp64rm.instrs.get(ins_name)
if sv_rm is not None:
dest_cr, src_cr, src_byname, dest_byname = decode_extra(sv_rm)
else:
log ("sv rm", sv_rm, dest_cr, src_cr, src_byname, dest_byname)
# see if srcstep/dststep need skipping over masked-out predicate bits
- if self.is_svp64_mode:
+ if (self.is_svp64_mode or ins_name == 'setvl' or
+ ins_name in ['svremap', 'svstate']):
yield from self.svstate_pre_inc()
+ if self.is_svp64_mode:
pre = yield from self.update_new_svstate_steps()
if pre:
self.svp64_reset_loop()
self.update_nia()
self.update_pc_next()
return
- srcstep, dststep = self.new_srcstep, self.new_dststep
+ srcstep, dststep = self.get_src_dststeps()
pred_dst_zero = self.pred_dst_zero
pred_src_zero = self.pred_src_zero
vl = self.svstate.vl
# for when SVREMAP is active, using pre-arranged schedule.
# note: modifying PowerDecoder2 needs to "settle"
remap_en = self.svstate.SVme
- active = self.last_op_svshape and remap_en != 0
+ persist = self.svstate.RMpst
+ active = (persist or self.last_op_svshape) and remap_en != 0
yield self.dec2.remap_active.eq(remap_en if active else 0)
yield Settle()
- if self.is_svp64_mode and self.last_op_svshape:
- # get four SVSHAPEs. here we are hard-coding
- SVSHAPE0 = self.spr['SVSHAPE0']
- SVSHAPE1 = self.spr['SVSHAPE1']
- SVSHAPE2 = self.spr['SVSHAPE2']
- SVSHAPE3 = self.spr['SVSHAPE3']
+ if persist or self.last_op_svshape:
+ remaps = self.get_remap_indices()
+ if self.is_svp64_mode and (persist or self.last_op_svshape):
# just some convenient debug info
for i in range(4):
sname = 'SVSHAPE%d' % i
(self.dec2.o_step, mo0), # RT
(self.dec2.o2_step, mo1), # EA
]
- # set up the iterators
- remaps = [(SVSHAPE0, SVSHAPE0.get_iterator()),
- (SVSHAPE1, SVSHAPE1.get_iterator()),
- (SVSHAPE2, SVSHAPE2.get_iterator()),
- (SVSHAPE3, SVSHAPE3.get_iterator()),
- ]
- # go through all iterators in lock-step, advance to next remap_idx
- remap_idxs = []
- for i, (shape, remap) in enumerate(remaps):
- # zero is "disabled"
- if shape.value == 0x0:
- remap_idxs.append(0)
- # pick src or dststep depending on reg num (0-2=in, 3-4=out)
- step = dststep if (i in [3, 4]) else srcstep
- # this is terrible. O(N^2) looking for the match. but hey.
- for idx, remap_idx in enumerate(remap):
- if idx == step:
- break
- remap_idxs.append(remap_idx)
-
+ remap_idxs = self.remap_idxs
rremaps = []
# now cross-index the required SHAPE for each of 3-in 2-out regs
rnames = ['RA', 'RB', 'RC', 'RT', 'EA']
yield dstep.eq(remap_idx)
# debug printout info
- rremaps.append((shape.mode, i, rnames[i], step, shape_idx,
+ rremaps.append((shape.mode, i, rnames[i], shape_idx,
remap_idx))
for x in rremaps:
log ("shape remap", x)
if not self.is_svp64_mode or not pred_src_zero:
log('reading reg %s %s' % (name, str(regnum)), is_vec)
if name in fregs:
- reg_val = self.fpr(regnum)
+ reg_val = SelectableInt(self.fpr(regnum))
elif name is not None:
- reg_val = self.gpr(regnum)
+ reg_val = SelectableInt(self.gpr(regnum))
else:
log('zero input reg %s %s' % (name, str(regnum)), is_vec)
reg_val = 0
inputs.append(reg_val)
# arrrrgh, awful hack, to get _RT into namespace
- if asmop == 'setvl':
+ if ins_name in ['setvl', 'svstep']:
regname = "_RT"
RT = yield self.dec2.dec.RT
self.namespace[regname] = SelectableInt(RT, 5)
+ if RT == 0:
+ self.namespace["RT"] = SelectableInt(0, 5)
+ regnum, is_vec = yield from get_pdecode_idx_out(self.dec2, "RT")
+ log('hack input reg %s %s' % (name, str(regnum)), is_vec)
# in SVP64 mode for LD/ST work out immediate
# XXX TODO: replace_ds for DS-Form rather than D-Form.
replace_d = False # update / replace constant in pseudocode
if self.is_svp64_mode:
ldstmode = yield self.dec2.rm_dec.ldstmode
- # bitreverse mode reads SVD (or SVDS - TODO)
+ # shift mode reads SVD (or SVDS - TODO)
# *BUT*... because this is "overloading" of LD operations,
# it gets *STORED* into D (or DS, TODO)
- if ldstmode == SVP64LDSTmode.BITREVERSE.value:
+ if ldstmode == SVP64LDSTmode.SHIFT.value:
imm = yield self.dec2.dec.fields.FormSVD.SVD[0:11]
imm = exts(imm, 11) # sign-extend to integer
- log ("bitrev SVD", imm)
+ log ("shift SVD", imm)
replace_d = True
else:
- imm = yield self.dec2.dec.fields.FormD.D[0:16]
+ if info.form == 'DS':
+ # DS-Form, multiply by 4 then knock 2 bits off after
+ imm = yield self.dec2.dec.fields.FormDS.DS[0:14] * 4
+ else:
+ imm = yield self.dec2.dec.fields.FormD.D[0:16]
imm = exts(imm, 16) # sign-extend to integer
# get the right step. LD is from srcstep, ST is dststep
op = yield self.dec2.e.do.insn_type
offsmul = 0
if op == MicrOp.OP_LOAD.value:
- offsmul = srcstep
- log("D-field src", imm, offsmul)
+ if remap_active:
+ offsmul = yield self.dec2.in1_step
+ log("D-field REMAP src", imm, offsmul)
+ else:
+ offsmul = srcstep
+ log("D-field src", imm, offsmul)
elif op == MicrOp.OP_STORE.value:
+ # XXX NOTE! no bit-reversed STORE! this should not ever be used
offsmul = dststep
log("D-field dst", imm, offsmul)
- # bit-reverse mode
- if ldstmode == SVP64LDSTmode.BITREVERSE.value:
+ # bit-reverse mode, rev already done through get_src_dst_steps()
+ if ldstmode == SVP64LDSTmode.SHIFT.value:
# manually look up RC, sigh
RC = yield self.dec2.dec.RC[0:5]
RC = self.gpr(RC)
- log ("RC", RC.value, "imm", imm, "offs", bin(offsmul),
- "rev", bin(bitrev(offsmul, vl)))
- imm = SelectableInt((imm * bitrev(offsmul, vl)) << RC.value, 32)
+ log ("LD-SHIFT:", "VL", vl,
+ "RC", RC.value, "imm", imm,
+ "offs", bin(offsmul),
+ )
+ imm = SelectableInt((imm * offsmul) << RC.value, 32)
# Unit-Strided LD/ST adds offset*width to immediate
elif ldstmode == SVP64LDSTmode.UNITSTRIDE.value:
ldst_len = yield self.dec2.e.do.data_len
elif ldstmode == SVP64LDSTmode.ELSTRIDE.value:
imm = SelectableInt(imm * offsmul, 32)
replace_d = True
- ldst_ra_vec = yield self.dec2.rm_dec.ldst_ra_vec
- ldst_imz_in = yield self.dec2.rm_dec.ldst_imz_in
- log("LDSTmode", ldstmode, SVP64LDSTmode.BITREVERSE.value,
- offsmul, imm, ldst_ra_vec, ldst_imz_in)
- # new replacement D
+ if replace_d:
+ ldst_ra_vec = yield self.dec2.rm_dec.ldst_ra_vec
+ ldst_imz_in = yield self.dec2.rm_dec.ldst_imz_in
+ log("LDSTmode", SVP64LDSTmode(ldstmode),
+ offsmul, imm, ldst_ra_vec, ldst_imz_in)
+ # new replacement D... errr.. DS
if replace_d:
- self.namespace['D'] = imm
+ if info.form == 'DS':
+ # TODO: assert 2 LSBs are zero?
+ log("DS-Form, TODO, assert 2 LSBs zero?", bin(imm.value))
+ imm.value = imm.value >> 2
+ self.namespace['DS'] = imm
+ else:
+ self.namespace['D'] = imm
# "special" registers
for special in info.special_regs:
# clear trap (trap) NIA
self.trap_nia = None
+ # check if this was an sv.bc* and create an indicator that
+ # this is the last check to be made as a loop. combined with
+ # the ALL/ANY mode we can early-exit
+ if self.is_svp64_mode and ins_name.startswith("sv.bc"):
+ no_in_vec = yield self.dec2.no_in_vec # BI is scalar
+ end_loop = no_in_vec or srcstep == vl-1 or dststep == vl-1
+ self.namespace['end_loop'] = SelectableInt(end_loop, 1)
+
# execute actual instruction here (finally)
log("inputs", inputs)
results = info.func(self, *inputs)
if not self.is_svp64_mode or not pred_dst_zero:
if hasattr(self.dec2.e.do, "rc"):
rc_en = yield self.dec2.e.do.rc.rc
- if rc_en:
+ if rc_en and ins_name not in ['svstep']:
regnum, is_vec = yield from get_pdecode_cr_out(self.dec2, "CR0")
self.handle_comparison(results, regnum)
# this is our Sub-Program-Counter loop from 0 to VL-1
pre = False
post = False
+ nia_update = True
if self.allow_next_step_inc:
- log("SVSTATE_NEXT: inc requested")
+ log("SVSTATE_NEXT: inc requested, mode",
+ self.svstate_next_mode, self.allow_next_step_inc)
yield from self.svstate_pre_inc()
pre = yield from self.update_new_svstate_steps()
if pre:
results = [SelectableInt(0, 64)]
self.handle_comparison(results) # CR0
else:
- log ("SVSTATE_NEXT: post-inc")
+ if self.allow_next_step_inc == 2:
+ log ("SVSTATE_NEXT: read")
+ nia_update = (yield from self.svstate_post_inc(ins_name))
+ else:
+ log ("SVSTATE_NEXT: post-inc")
+ # use actual src/dst-step here to check end, do NOT
+ # use bit-reversed version
srcstep, dststep = self.new_srcstep, self.new_dststep
+ remaps = self.get_remap_indices()
+ remap_idxs = self.remap_idxs
vl = self.svstate.vl
end_src = srcstep == vl-1
end_dst = dststep == vl-1
- if not end_src:
- self.svstate.srcstep += SelectableInt(1, 7)
- if not end_dst:
- self.svstate.dststep += SelectableInt(1, 7)
+ if self.allow_next_step_inc != 2:
+ if not end_src:
+ self.svstate.srcstep += SelectableInt(1, 7)
+ if not end_dst:
+ self.svstate.dststep += SelectableInt(1, 7)
self.namespace['SVSTATE'] = self.svstate.spr
# set CR0 (if Rc=1) based on end
if rc_en:
srcstep = self.svstate.srcstep
dststep = self.svstate.srcstep
- endtest = 0 if (end_src or end_dst) else 1
- results = [SelectableInt(endtest, 64)]
- self.handle_comparison(results) # CR0
+ endtest = 1 if (end_src or end_dst) else 0
+ #results = [SelectableInt(endtest, 64)]
+ #self.handle_comparison(results) # CR0
+
+ # see if svstep was requested, if so, which SVSTATE
+ endings = 0b111
+ if self.svstate_next_mode > 0:
+ shape_idx = self.svstate_next_mode.value-1
+ endings = self.remap_loopends[shape_idx]
+ cr_field = SelectableInt((~endings)<<1 | endtest, 4)
+ print ("svstep Rc=1, CR0", cr_field)
+ self.crl[0].eq(cr_field) # CR0
if end_src or end_dst:
# reset at end of loop including exit Vertical Mode
log ("SVSTATE_NEXT: after increments, reset")
self.svstate.vfirst = 0
elif self.is_svp64_mode:
- yield from self.svstate_post_inc()
+ nia_update = (yield from self.svstate_post_inc(ins_name))
else:
# XXX only in non-SVP64 mode!
# record state of whether the current operation was an svshape,
# to interrupt in between. sigh.
self.last_op_svshape = asmop == 'svremap'
- self.update_pc_next()
+ if nia_update:
+ self.update_pc_next()
- def SVSTATE_NEXT(self):
+ def SVSTATE_NEXT(self, mode, submode):
"""explicitly moves srcstep/dststep on to next element, for
"Vertical-First" mode. this function is called from
setvl pseudo-code, as a pseudo-op "svstep"
+
+ WARNING: this function uses information that was created EARLIER
+ due to it being in the middle of a yield, but this function is
+ *NOT* called from yield (it's called from compiled pseudocode).
"""
- log("SVSTATE_NEXT")
- self.allow_next_step_inc = True
+ self.allow_next_step_inc = submode.value + 1
+ log("SVSTATE_NEXT mode", mode, submode, self.allow_next_step_inc)
+ self.svstate_next_mode = mode
+ if self.svstate_next_mode > 0:
+ shape_idx = self.svstate_next_mode.value-1
+ return SelectableInt(self.remap_idxs[shape_idx], 7)
+ return SelectableInt(0, 7)
def svstate_pre_inc(self):
"""check if srcstep/dststep need to skip over masked-out predicate bits
sv_a_nz = yield self.dec2.sv_a_nz
fft_mode = yield self.dec2.use_svp64_fft
in1 = yield self.dec2.e.read_reg1.data
- log ("SVP64: VL, srcstep, dststep, sv_a_nz, in1 fft",
- vl, srcstep, dststep, sv_a_nz, in1, fft_mode)
+ log ("SVP64: VL, srcstep, dststep, sv_a_nz, in1 fft, svp64",
+ vl, srcstep, dststep, sv_a_nz, in1, fft_mode,
+ self.is_svp64_mode)
# get predicate mask
srcmask = dstmask = 0xffff_ffff_ffff_ffff
log (" new srcstep", srcstep)
log (" new dststep", dststep)
+ def get_src_dststeps(self):
+ """gets srcstep and dststep
+ """
+ return self.new_srcstep, self.new_dststep
+
def update_new_svstate_steps(self):
+ # note, do not get the bit-reversed srcstep here!
srcstep, dststep = self.new_srcstep, self.new_dststep
# update SVSTATE with new srcstep
# nothing needs doing (TODO zeroing): just do next instruction
return srcstep == vl or dststep == vl
- def svstate_post_inc(self, vf=0):
+ def svstate_post_inc(self, insn_name, vf=0):
# check if SV "Vertical First" mode is enabled
vfirst = self.svstate.vfirst
log (" SV Vertical First", vf, vfirst)
svp64_is_vector = (out_vec or in_vec)
else:
svp64_is_vector = out_vec
+ # check if this was an sv.bc* and if so did it succeed
+ if self.is_svp64_mode and insn_name.startswith("sv.bc"):
+ end_loop = self.namespace['end_loop']
+ log("branch %s end_loop" % insn_name, end_loop)
+ if end_loop.value:
+ self.svp64_reset_loop()
+ self.update_pc_next()
+ return False
if svp64_is_vector and srcstep != vl-1 and dststep != vl-1:
self.svstate.srcstep += SelectableInt(1, 7)
self.svstate.dststep += SelectableInt(1, 7)
+ self.namespace['SVSTATE'] = self.svstate
+ # not an SVP64 branch, so fix PC (NIA==CIA) for next loop
+ # (by default, NIA is CIA+4 if v3.0B or CIA+8 if SVP64)
+ # this way we keep repeating the same instruction (with new steps)
self.pc.NIA.value = self.pc.CIA.value
self.namespace['NIA'] = self.pc.NIA
- self.namespace['SVSTATE'] = self.svstate
log("end of sub-pc call", self.namespace['CIA'],
self.namespace['NIA'])
return False # DO NOT allow PC update whilst Sub-PC loop running
self.pc.update_nia(self.is_svp64_mode)
self.namespace['NIA'] = self.pc.NIA
+
def inject():
"""Decorator factory.
log("args[0]", args[0].namespace['CIA'],
args[0].namespace['NIA'],
args[0].namespace['SVSTATE'])
+ if 'end_loop' in func_globals:
+ log("args[0] end_loop", func_globals['end_loop'])
args[0].namespace = func_globals
#exec (func.__code__, func_globals)
projects / openpower-isa.git / blobdiff