sigh, I-DCT had to reverse the order of middle loop to stop

[openpower-isa.git] / src / openpower / decoder / isa / fastdct-test.py

diff --git a/src/openpower/decoder/isa/fastdct-test.py b/src/openpower/decoder/isa/fastdct-test.py
index be786aa5f4b18bd617c5168dc30f5f1e907a0d08..d9031813d31ae39fb7dab48dc46c57857b12c2ee 100644 (file)
--- a/src/openpower/decoder/isa/fastdct-test.py
+++ b/src/openpower/decoder/isa/fastdct-test.py
@@ -28,7 +28,7 @@ import fastdctlee, naivedct, remap_dct_yield
 class FastDctTest(unittest.TestCase):
 
     def test_fast_dct_lee_vs_naive(self):
-        for i in range(2, 3):
+        for i in range(3, 8):
             n = 2**i
             vector = FastDctTest.nonrandom_vector(n)
             expect = naivedct.transform(vector)