class MemException(Exception):
pass
+def process_mem(initial_mem, row_bytes=8):
+ res = {}
+ # different types of memory data structures recognised (for convenience)
+ if isinstance(initial_mem, list):
+ initial_mem = (0, initial_mem)
+ if isinstance(initial_mem, tuple):
+ startaddr, mem = initial_mem
+ initial_mem = {}
+ for i, val in enumerate(mem):
+ initial_mem[startaddr + row_bytes*i] = (val, row_bytes)
+
+ for addr, val in initial_mem.items():
+ if isinstance(val, tuple):
+ (val, width) = val
+ else:
+ width = row_bytes # assume same width
+ #val = swap_order(val, width)
+ res[addr] = (val, width)
+
+ return res
+
class Mem:
self.mem = {}
self.bytes_per_word = row_bytes
self.word_log2 = math.ceil(math.log2(row_bytes))
+ self.last_ld_addr = None
+ self.last_st_addr = None
log("Sim-Mem", initial_mem, self.bytes_per_word, self.word_log2)
if not initial_mem:
return
- # different types of memory data structures recognised (for convenience)
- if isinstance(initial_mem, list):
- initial_mem = (0, initial_mem)
- if isinstance(initial_mem, tuple):
- startaddr, mem = initial_mem
- initial_mem = {}
- for i, val in enumerate(mem):
- initial_mem[startaddr + row_bytes*i] = (val, row_bytes)
-
- for addr, val in initial_mem.items():
- if isinstance(val, tuple):
- (val, width) = val
- else:
- width = row_bytes # assume same width
+ for addr, (val, width) in process_mem(initial_mem, row_bytes).items():
#val = swap_order(val, width)
self.st(addr, val, width, swap=False)
instr_fetch=False):
log("ld from addr 0x%x width %d" % (address, width),
swap, check_in_mem, instr_fetch)
+ self.last_ld_addr = address # record last load
ldaddr = address
remainder = address & (self.bytes_per_word - 1)
address = address >> self.word_log2
def st(self, addr, v, width=8, swap=True):
staddr = addr
+ self.last_st_addr = addr # record last store
remainder = addr & (self.bytes_per_word - 1)
addr = addr >> self.word_log2
log("Writing 0x%x to ST 0x%x memaddr 0x%x/%x swap %s" % \