add mm=1 svindex test, setting single targetted SVSHAPE

[openpower-isa.git] / src / openpower / decoder / isa / mem.py

diff --git a/src/openpower/decoder/isa/mem.py b/src/openpower/decoder/isa/mem.py
index 36d6e8444c4b10cb72e3eb6e1463e0a38b19158a..c41e436e5e5133a6bebaf76b9df81d4d60baa51c 100644 (file)
--- a/src/openpower/decoder/isa/mem.py
+++ b/src/openpower/decoder/isa/mem.py
@@ -31,6 +31,27 @@ def swap_order(x, nbytes):
 class MemException(Exception):
     pass
 
+def process_mem(initial_mem, row_bytes=8):
+    res = {}
+    # different types of memory data structures recognised (for convenience)
+    if isinstance(initial_mem, list):
+        initial_mem = (0, initial_mem)
+    if isinstance(initial_mem, tuple):
+        startaddr, mem = initial_mem
+        initial_mem = {}
+        for i, val in enumerate(mem):
+            initial_mem[startaddr + row_bytes*i] = (val, row_bytes)
+
+    for addr, val in initial_mem.items():
+        if isinstance(val, tuple):
+            (val, width) = val
+        else:
+            width = row_bytes # assume same width
+        #val = swap_order(val, width)
+        res[addr] = (val, width)
+
+    return res
+
 
 class Mem:
 
@@ -38,24 +59,13 @@ class Mem:
         self.mem = {}
         self.bytes_per_word = row_bytes
         self.word_log2 = math.ceil(math.log2(row_bytes))
+        self.last_ld_addr = None
+        self.last_st_addr = None
         log("Sim-Mem", initial_mem, self.bytes_per_word, self.word_log2)
         if not initial_mem:
             return
 
-        # different types of memory data structures recognised (for convenience)
-        if isinstance(initial_mem, list):
-            initial_mem = (0, initial_mem)
-        if isinstance(initial_mem, tuple):
-            startaddr, mem = initial_mem
-            initial_mem = {}
-            for i, val in enumerate(mem):
-                initial_mem[startaddr + row_bytes*i] = (val, row_bytes)
-
-        for addr, val in initial_mem.items():
-            if isinstance(val, tuple):
-                (val, width) = val
-            else:
-                width = row_bytes # assume same width
+        for addr, (val, width) in process_mem(initial_mem, row_bytes).items():
             #val = swap_order(val, width)
             self.st(addr, val, width, swap=False)
 
@@ -74,6 +84,7 @@ class Mem:
                  instr_fetch=False):
         log("ld from addr 0x%x width %d" % (address, width),
                 swap, check_in_mem, instr_fetch)
+        self.last_ld_addr = address # record last load
         ldaddr = address
         remainder = address & (self.bytes_per_word - 1)
         address = address >> self.word_log2
@@ -101,6 +112,7 @@ class Mem:
 
     def st(self, addr, v, width=8, swap=True):
         staddr = addr
+        self.last_st_addr = addr # record last store
         remainder = addr & (self.bytes_per_word - 1)
         addr = addr >> self.word_log2
         log("Writing 0x%x to ST 0x%x memaddr 0x%x/%x swap %s" % \