from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
import sys
import getopt
import struct
val = mem.ld(addr, 8)
f.write(struct.pack('>Q', val)) # unsigned long
-def sim_check_data(simulator, qemu, check_addr):
+def sim_check_data(simulator, qemu, check_addr, msg):
addr = check_addr & ~0x7 # align
sim_data = simulator.mem.ld(addr, 8, swap=False)
qdata = qemu.get_mem(addr, 8)[0]
initial_regs=initial_regs, initial_fprs=initial_fprs)
for reg, val in qemu._get_registers().items():
log ("qemu reg", reg, hex(val))
+ if True:
+ offs, length = 0x200000, 0x200
+ qmem = qemu.get_mem(offs, length)
+ log("qemu mem pre-dump", hex(offs), length)
+ for i, data in enumerate(qmem):
+ log(hex(offs+i*8), hex(data))
m = Module()
comb = m.d.comb
check_addr = simulator.last_ld_addr
msg = "ld"
if check_addr is not None:
- sim_check_data(simulator, qemu, check_addr)
+ sim_check_data(simulator, qemu, check_addr, msg)
+ sim_check_data(simulator, qemu, 0x600800, "dbgld")
if _pc is None:
break
def run_simulation():
binaryname = None
- initial_regs = [0]*32
- initial_fprs = [0]*32
+ initial_regs = [0]*128
+ initial_fprs = [0]*128
initial_sprs = None
initial_mem = {}
initial_pc = 0x0
elif opt in ['-a', '--listing']:
lst = arg
elif opt in ['-g', '--intregs']:
- initial_regs = read_entries(arg, 32)
+ initial_regs = read_entries(arg, 128)
elif opt in ['-f', '--fpregs']:
- initial_fprs = read_entries(arg, 32)
+ initial_fprs = read_entries(arg, 128)
elif opt in ['-s', '--sprs']:
initial_sprs = read_entries(arg, 32)
elif opt in ['-l', '--load']: