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fix setvl. not setting CR0 properly
[openpower-isa.git]
/
src
/
openpower
/
decoder
/
isa
/
pypowersim.py
diff --git
a/src/openpower/decoder/isa/pypowersim.py
b/src/openpower/decoder/isa/pypowersim.py
index cb7964fc84384acb429972eb839f7751a2022ba7..20edf56560b248df965d17cb6430a7803e2e3737 100644
(file)
--- a/
src/openpower/decoder/isa/pypowersim.py
+++ b/
src/openpower/decoder/isa/pypowersim.py
@@
-1,5
+1,5
@@
from nmigen import Module, Signal
-from nmigen.
back.py
sim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
import sys
import getopt
import struct