no python files to be committed in isafunctions

[openpower-isa.git] / src / openpower / decoder / isa / pypowersim.py

diff --git a/src/openpower/decoder/isa/pypowersim.py b/src/openpower/decoder/isa/pypowersim.py
index 040fb64dfa38fe03a481036aaa8ef599be9232ed..cb7964fc84384acb429972eb839f7751a2022ba7 100644 (file)
--- a/src/openpower/decoder/isa/pypowersim.py
+++ b/src/openpower/decoder/isa/pypowersim.py
@@ -37,6 +37,14 @@ def write_data(mem, fname, offset, sz):
             val = mem.ld(addr, 8)
             f.write(struct.pack('>Q', val)) # unsigned long
 
+def sim_check_data(simulator, qemu, check_addr, msg):
+    addr = check_addr & ~0x7 # align
+    sim_data = simulator.mem.ld(addr, 8, swap=False)
+    qdata = qemu.get_mem(addr, 8)[0]
+    log ("last", msg, hex(check_addr), hex(sim_data), hex(qdata))
+    if sim_data != qdata:
+        log("expect mem %x, %x got %x" % (addr, qdata, sim_data))
+        exit(0)
 
 def convert_to_num(num):
     # detect number types
@@ -141,6 +149,12 @@ def run_tst(args, generator, qemu,
                 initial_regs=initial_regs, initial_fprs=initial_fprs)
         for reg, val in qemu._get_registers().items():
             log ("qemu reg", reg, hex(val))
+        if True:
+            offs, length = 0x200000, 0x200
+            qmem = qemu.get_mem(offs, length)
+            log("qemu mem pre-dump", hex(offs), length)
+            for i, data in enumerate(qmem):
+                log(hex(offs+i*8), hex(data))
 
     m = Module()
     comb = m.d.comb
@@ -224,6 +238,17 @@ def run_tst(args, generator, qemu,
             if not _pc or simulator.halted:
                 qemu.set_endian(False)
             qemu_register_compare(simulator, qemu, range(32), range(32))
+            # check last store address
+            check_addr = None
+            if simulator.last_st_addr is not None:
+                check_addr = simulator.last_st_addr
+                msg = "st"
+            if simulator.last_ld_addr is not None:
+                check_addr = simulator.last_ld_addr
+                msg = "ld"
+            if check_addr is not None:
+                sim_check_data(simulator, qemu, check_addr, msg)
+            sim_check_data(simulator, qemu, 0x600800, "dbgld")
             if _pc is None:
                 break
 
@@ -259,8 +284,8 @@ def help():
 def run_simulation():
 
     binaryname = None
-    initial_regs = [0]*32
-    initial_fprs = [0]*32
+    initial_regs = [0]*128
+    initial_fprs = [0]*128
     initial_sprs = None
     initial_mem = {}
     initial_pc = 0x0
@@ -291,9 +316,9 @@ def run_simulation():
         elif opt in ['-a', '--listing']:
             lst = arg
         elif opt in ['-g', '--intregs']:
-            initial_regs = read_entries(arg, 32)
+            initial_regs = read_entries(arg, 128)
         elif opt in ['-f', '--fpregs']:
-            initial_fprs = read_entries(arg, 32)
+            initial_fprs = read_entries(arg, 128)
         elif opt in ['-s', '--sprs']:
             initial_sprs = read_entries(arg, 32)
         elif opt in ['-l', '--load']:
@@ -352,10 +377,13 @@ def run_simulation():
             write_data(simulator.mem, fname, offs, length)
             if qemu:
                 qmem = qemu.get_mem(offs, length)
+                log("qemu mem", hex(offs), length)
                 for i, mem in enumerate(qmem):
                     log(hex(offs+i*8), hex(mem))
-                for reg, val in qemu._get_registers().items():
-                    log ("qemu reg", reg, hex(val))
+        if qemu:
+            log("final complete qemu reg dump")
+            for reg, val in qemu._get_registers().items():
+                log ("qemu reg", reg, hex(val))
 
         # cleanup
         if qemu: