fix setvl. not setting CR0 properly

[openpower-isa.git] / src / openpower / decoder / isa / svstate.py

diff --git a/src/openpower/decoder/isa/svstate.py b/src/openpower/decoder/isa/svstate.py
index 6127b25b716ef26f15f99af80fd00d1bb5923110..9b8c89be9cbf5227dde3f208ed645e8020b2a05d 100644 (file)
--- a/src/openpower/decoder/isa/svstate.py
+++ b/src/openpower/decoder/isa/svstate.py
@@ -1,7 +1,6 @@
-from openpower.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
-                                        selectconcat)
-from openpower.decoder.isa.remapyield import iterate_indices
-from openpower.decoder.isa.remap_fft_yield import iterate_butterfly_indices
+from openpower.decoder.selectable_int import (FieldSelectableInt,
+                                              SelectableInt,
+                                                )
 from openpower.sv.svstate import SVSTATERec
 import os
 from copy import deepcopy
@@ -56,6 +55,22 @@ class SVP64State(SelectableInt):
     def srcstep(self, value):
         self.fsi['srcstep'].eq(value)
 
+    @property
+    def dsubstep(self):
+        return self.fsi['dsubstep'].asint(msb0=True)
+
+    @dsubstep.setter
+    def dsubstep(self, value):
+        self.fsi['dsubstep'].eq(value)
+
+    @property
+    def ssubstep(self):
+        return self.fsi['ssubstep'].asint(msb0=True)
+
+    @ssubstep.setter
+    def ssubstep(self, value):
+        self.fsi['ssubstep'].eq(value)
+
     @property
     def subvl(self):
         return self.fsi['subvl'].asint(msb0=True)
@@ -112,3 +127,19 @@ class SVP64State(SelectableInt):
     def SVme(self, value):
         self.fsi['SVme'].eq(value)
 
+    @property
+    def vfirst(self):
+        return self.fsi['vfirst'].asint(msb0=True)
+
+    @vfirst.setter
+    def vfirst(self, value):
+        self.fsi['vfirst'].eq(value)
+
+    @property
+    def RMpst(self):
+        return self.fsi['RMpst'].asint(msb0=True)
+
+    @RMpst.setter
+    def RMpst(self, value):
+        self.fsi['RMpst'].eq(value)
+