-from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
from nmutil.formaltest import FHDLTestCase
import unittest
-from soc.decoder.isa.caller import ISACaller
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.simulator.program import Program
-from soc.decoder.isa.caller import ISACaller, inject
-from soc.decoder.selectable_int import SelectableInt
-from soc.decoder.orderedset import OrderedSet
-from soc.decoder.isa.all import ISA
-
-
-class Register:
- def __init__(self, num):
- self.num = num
-
-def run_tst(generator, initial_regs, initial_sprs=None, svstate=0, mmu=False,
- initial_cr=0,mem=None):
- if initial_sprs is None:
- initial_sprs = {}
- m = Module()
- comb = m.d.comb
- instruction = Signal(32)
-
- pdecode = create_pdecode()
-
- gen = list(generator.generate_instructions())
- insncode = generator.assembly.splitlines()
- instructions = list(zip(gen, insncode))
-
- m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
- simulator = ISA(pdecode2, initial_regs, initial_sprs, initial_cr,
- initial_insns=gen, respect_pc=True,
- initial_svstate=svstate,
- initial_mem=mem,
- disassembly=insncode,
- bigendian=0,
- mmu=mmu)
- comb += pdecode2.dec.raw_opcode_in.eq(instruction)
- sim = Simulator(m)
-
-
- def process():
-
- yield pdecode2.dec.bigendian.eq(0) # little / big?
- pc = simulator.pc.CIA.value
- index = pc//4
- while index < len(instructions):
- print("instr pc", pc)
- try:
- yield from simulator.setup_one()
- except KeyError: # indicates instruction not in imem: stop
- break
- yield Settle()
-
- ins, code = instructions[index]
- print(" 0x{:X}".format(ins & 0xffffffff))
- opname = code.split(' ')[0]
- print(code, opname)
-
- # ask the decoder to decode this binary data (endian'd)
- yield from simulator.execute_one()
- pc = simulator.pc.CIA.value
- index = pc//4
-
- sim.add_process(process)
- with sim.write_vcd("simulator.vcd", "simulator.gtkw",
- traces=[]):
- sim.run()
- return simulator
+from openpower.simulator.program import Program
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.decoder.isa.test_runner import (Register, ISATestRunner,
+ run_tst)
class DecoderTestCase(FHDLTestCase):
print("cr", sim.cr)
expected = (7-i)
# check CR[0]/1/2/3 as well
- print("cr%d", sim.crl[i])
+ print("cr%d" % i, sim.crl[i].asint(True))
self.assertTrue(SelectableInt(expected, 4) == sim.crl[i])
# check CR itself
- self.assertEqual(sim.cr, SelectableInt(expected << ((7-i)*4), 32))
+ self.assertEqual(sim.cr, SelectableInt(expected << ((7-i)*4), 64))
def run_tst_program(self, prog, initial_regs=[0] * 32):
simulator = run_tst(prog, initial_regs)