add gpr lookup in Indexed SVSHAPE iterator (no elwidths yet)

[openpower-isa.git] / src / openpower / decoder / isa / test_caller.py

diff --git a/src/openpower/decoder/isa/test_caller.py b/src/openpower/decoder/isa/test_caller.py
index efb6275fefef697a6200df3db21ca3094658a654..5fa7fbeb00a076e6c9dbc9a0a8b740e28b0e73da 100644 (file)
--- a/src/openpower/decoder/isa/test_caller.py
+++ b/src/openpower/decoder/isa/test_caller.py
@@ -1,76 +1,9 @@
-from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
-from openpower.decoder.isa.caller import ISACaller
-from openpower.decoder.power_decoder import (create_pdecode)
-from openpower.decoder.power_decoder2 import (PowerDecode2)
 from openpower.simulator.program import Program
-from openpower.decoder.isa.caller import ISACaller, inject
 from openpower.decoder.selectable_int import SelectableInt
-from openpower.decoder.orderedset import OrderedSet
-from openpower.decoder.isa.all import ISA
-
-
-class Register:
-    def __init__(self, num):
-        self.num = num
-
-def run_tst(generator, initial_regs, initial_sprs=None, svstate=0, mmu=False,
-                                     initial_cr=0, mem=None,
-                                     initial_fprs=None):
-    if initial_sprs is None:
-        initial_sprs = {}
-    m = Module()
-    comb = m.d.comb
-    instruction = Signal(32)
-
-    pdecode = create_pdecode()
-
-    gen = list(generator.generate_instructions())
-    insncode = generator.assembly.splitlines()
-    instructions = list(zip(gen, insncode))
-
-    m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
-    simulator = ISA(pdecode2, initial_regs, initial_sprs, initial_cr,
-                    initial_insns=gen, respect_pc=True,
-                    initial_svstate=svstate,
-                    initial_mem=mem,
-                    fpregfile=initial_fprs,
-                    disassembly=insncode,
-                    bigendian=0,
-                    mmu=mmu)
-    comb += pdecode2.dec.raw_opcode_in.eq(instruction)
-    sim = Simulator(m)
-
-    def process():
-
-        yield pdecode2.dec.bigendian.eq(0)  # little / big?
-        pc = simulator.pc.CIA.value
-        index = pc//4
-        while index < len(instructions):
-            print("instr pc", pc)
-            try:
-                yield from simulator.setup_one()
-            except KeyError:  # indicates instruction not in imem: stop
-                break
-            yield Settle()
-
-            ins, code = instructions[index]
-            print("    0x{:X}".format(ins & 0xffffffff))
-            opname = code.split(' ')[0]
-            print(code, opname)
-
-            # ask the decoder to decode this binary data (endian'd)
-            yield from simulator.execute_one()
-            pc = simulator.pc.CIA.value
-            index = pc//4
-
-    sim.add_process(process)
-    with sim.write_vcd("simulator.vcd", "simulator.gtkw",
-                       traces=[]):
-        sim.run()
-    return simulator
+from openpower.decoder.isa.test_runner import (Register, ISATestRunner,
+                                              run_tst)
 
 
 class DecoderTestCase(FHDLTestCase):