+import random
import re
-from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Settle
from nmutil.formaltest import FHDLTestCase
import unittest
-from openpower.decoder.isa.caller import ISACaller
+
from openpower.decoder.power_decoder import create_pdecode
from openpower.decoder.power_decoder2 import (PowerDecode2)
from openpower.simulator.program import Program
-from openpower.decoder.isa.caller import ISACaller, inject
from openpower.decoder.selectable_int import SelectableInt
-from openpower.decoder.orderedset import OrderedSet
-from openpower.decoder.isa.all import ISA
+
+from openpower.decoder.isa.test_runner import run_tst
# PowerISA Version 3.0C Book 1 App. B, Table 129
+DPD_TO_BCD_TABLE = """
+ 0 1 2 3 4 5 6 7 8 9 A B C D E F
+00_ 000 001 002 003 004 005 006 007 008 009 080 081 800 801 880 881
+01_ 010 011 012 013 014 015 016 017 018 019 090 091 810 811 890 891
+02_ 020 021 022 023 024 025 026 027 028 029 082 083 820 821 808 809
+03_ 030 031 032 033 034 035 036 037 038 039 092 093 830 831 818 819
+04_ 040 041 042 043 044 045 046 047 048 049 084 085 840 841 088 089
+05_ 050 051 052 053 054 055 056 057 058 059 094 095 850 851 098 099
+06_ 060 061 062 063 064 065 066 067 068 069 086 087 860 861 888 889
+07_ 070 071 072 073 074 075 076 077 078 079 096 097 870 871 898 899
+08_ 100 101 102 103 104 105 106 107 108 109 180 181 900 901 980 981
+09_ 110 111 112 113 114 115 116 117 118 119 190 191 910 911 990 991
+0A_ 120 121 122 123 124 125 126 127 128 129 182 183 920 921 908 909
+0B_ 130 131 132 133 134 135 136 137 138 139 192 193 930 931 918 919
+0C_ 140 141 142 143 144 145 146 147 148 149 184 185 940 941 188 189
+0D_ 150 151 152 153 154 155 156 157 158 159 194 195 950 951 198 199
+0E_ 160 161 162 163 164 165 166 167 168 169 186 187 960 961 988 989
+0F_ 170 171 172 173 174 175 176 177 178 179 196 197 970 971 998 999
+10_ 200 201 202 203 204 205 206 207 208 209 280 281 802 803 882 883
+11_ 210 211 212 213 214 215 216 217 218 219 290 291 812 813 892 893
+12_ 220 221 222 223 224 225 226 227 228 229 282 283 822 823 828 829
+13_ 230 231 232 233 234 235 236 237 238 239 292 293 832 833 838 839
+14_ 240 241 242 243 244 245 246 247 248 249 284 285 842 843 288 289
+15_ 250 251 252 253 254 255 256 257 258 259 294 295 852 853 298 299
+16_ 260 261 262 263 264 265 266 267 268 269 286 287 862 863 (888) (889)
+17_ 270 271 272 273 274 275 276 277 278 279 296 297 872 873 (898) (899)
+18_ 300 301 302 303 304 305 306 307 308 309 380 381 902 903 982 983
+19_ 310 311 312 313 314 315 316 317 318 319 390 391 912 913 992 993
+1A_ 320 321 322 323 324 325 326 327 328 329 382 383 922 923 928 929
+1B_ 330 331 332 333 334 335 336 337 338 339 392 393 932 933 938 939
+1C_ 340 341 342 343 344 345 346 347 348 349 384 385 942 943 388 389
+1D_ 350 351 352 353 354 355 356 357 358 359 394 395 952 953 398 399
+1E_ 360 361 362 363 364 365 366 367 368 369 386 387 962 963 (988) (989)
+1F_ 370 371 372 373 374 375 376 377 378 379 396 397 972 973 (998) (999)
+20_ 400 401 402 403 404 405 406 407 408 409 480 481 804 805 884 885
+21_ 410 411 412 413 414 415 416 417 418 419 490 491 814 815 894 895
+22_ 420 421 422 423 424 425 426 427 428 429 482 483 824 825 848 849
+23_ 430 431 432 433 434 435 436 437 438 439 492 493 834 835 858 859
+24_ 440 441 442 443 444 445 446 447 448 449 484 485 844 845 488 489
+25_ 450 451 452 453 454 455 456 457 458 459 494 495 854 855 498 499
+26_ 460 461 462 463 464 465 466 467 468 469 486 487 864 865 (888) (889)
+27_ 470 471 472 473 474 475 476 477 478 479 496 497 874 875 (898) (899)
+28_ 500 501 502 503 504 505 506 507 508 509 580 581 904 905 984 985
+29_ 510 511 512 513 514 515 516 517 518 519 590 591 914 915 994 995
+2A_ 520 521 522 523 524 525 526 527 528 529 582 583 924 925 948 949
+2B_ 530 531 532 533 534 535 536 537 538 539 592 593 934 935 958 959
+2C_ 540 541 542 543 544 545 546 547 548 549 584 585 944 945 588 589
+2D_ 550 551 552 553 554 555 556 557 558 559 594 595 954 955 598 599
+2E_ 560 561 562 563 564 565 566 567 568 569 586 587 964 965 (988) (989)
+2F_ 570 571 572 573 574 575 576 577 578 579 596 597 974 975 (998) (999)
+30_ 600 601 602 603 604 605 606 607 608 609 680 681 806 807 886 887
+31_ 610 611 612 613 614 615 616 617 618 619 690 691 816 817 896 897
+32_ 620 621 622 623 624 625 626 627 628 629 682 683 826 827 868 869
+33_ 630 631 632 633 634 635 636 637 638 639 692 693 836 837 878 879
+34_ 640 641 642 643 644 645 646 647 648 649 684 685 846 847 688 689
+35_ 650 651 652 653 654 655 656 657 658 659 694 695 856 857 698 699
+36_ 660 661 662 663 664 665 666 667 668 669 686 687 866 867 (888) (889)
+37_ 670 671 672 673 674 675 676 677 678 679 696 697 876 877 (898) (899)
+38_ 700 701 702 703 704 705 706 707 708 709 780 781 906 907 986 987
+39_ 710 711 712 713 714 715 716 717 718 719 790 791 916 917 996 997
+3A_ 720 721 722 723 724 725 726 727 728 729 782 783 926 927 968 969
+3B_ 730 731 732 733 734 735 736 737 738 739 792 793 936 937 978 979
+3C_ 740 741 742 743 744 745 746 747 748 749 784 785 946 947 788 789
+3D_ 750 751 752 753 754 755 756 757 758 759 794 795 956 957 798 799
+3E_ 760 761 762 763 764 765 766 767 768 769 786 787 966 967 (988) (989)
+3F_ 770 771 772 773 774 775 776 777 778 779 796 797 976 977 (998) (999)
+"""
+DPD_TO_BCD_PATTERN = (r"^([0-9A-F]{2})_\s+" +
+ r"\s+".join([r"\(?(\d{3})\)?"] * 16) +
+ r"$")
+DPD_TO_BCD_REGEX = re.compile(DPD_TO_BCD_PATTERN, re.M)
+
+
BCD_TO_DPD_TABLE = """
0 1 2 3 4 5 6 7 8 9
00_ 000 001 002 003 004 005 006 007 008 009
98_ 08E 08F 18E 18F 28E 28F 38E 38F 0EE 0EF
99_ 09E 09F 19E 19F 29E 29F 39E 39F 0FE 0FF
"""
-BCD_TO_DPD_PATTERN = (r"^(\d{2})_\s" + r"\s".join([r"([0-9A-F]{3})"] * 10) + r"$")
+BCD_TO_DPD_PATTERN = (r"^(\d{2})_\s" +
+ r"\s".join([r"([0-9A-F]{3})"] * 10) +
+ r"$")
BCD_TO_DPD_REGEX = re.compile(BCD_TO_DPD_PATTERN, re.M)
-DPD_TO_BCD_TABLE = """
- 0 1 2 3 4 5 6 7 8 9 A B C D E F
-00_ 000 001 002 003 004 005 006 007 008 009 080 081 800 801 880 881
-01_ 010 011 012 013 014 015 016 017 018 019 090 091 810 811 890 891
-02_ 020 021 022 023 024 025 026 027 028 029 082 083 820 821 808 809
-03_ 030 031 032 033 034 035 036 037 038 039 092 093 830 831 818 819
-04_ 040 041 042 043 044 045 046 047 048 049 084 085 840 841 088 089
-05_ 050 051 052 053 054 055 056 057 058 059 094 095 850 851 098 099
-06_ 060 061 062 063 064 065 066 067 068 069 086 087 860 861 888 889
-07_ 070 071 072 073 074 075 076 077 078 079 096 097 870 871 898 899
-08_ 100 101 102 103 104 105 106 107 108 109 180 181 900 901 980 981
-09_ 110 111 112 113 114 115 116 117 118 119 190 191 910 911 990 991
-0A_ 120 121 122 123 124 125 126 127 128 129 182 183 920 921 908 909
-0B_ 130 131 132 133 134 135 136 137 138 139 192 193 930 931 918 919
-0C_ 140 141 142 143 144 145 146 147 148 149 184 185 940 941 188 189
-0D_ 150 151 152 153 154 155 156 157 158 159 194 195 950 951 198 199
-0E_ 160 161 162 163 164 165 166 167 168 169 186 187 960 961 988 989
-0F_ 170 171 172 173 174 175 176 177 178 179 196 197 970 971 998 999
-10_ 200 201 202 203 204 205 206 207 208 209 280 281 802 803 882 883
-11_ 210 211 212 213 214 215 216 217 218 219 290 291 812 813 892 893
-12_ 220 221 222 223 224 225 226 227 228 229 282 283 822 823 828 829
-13_ 230 231 232 233 234 235 236 237 238 239 292 293 832 833 838 839
-14_ 240 241 242 243 244 245 246 247 248 249 284 285 842 843 288 289
-15_ 250 251 252 253 254 255 256 257 258 259 294 295 852 853 298 299
-16_ 260 261 262 263 264 265 266 267 268 269 286 287 862 863 (888) (889)
-17_ 270 271 272 273 274 275 276 277 278 279 296 297 872 873 (898) (899)
-18_ 300 301 302 303 304 305 306 307 308 309 380 381 902 903 982 983
-19_ 310 311 312 313 314 315 316 317 318 319 390 391 912 913 992 993
-1A_ 320 321 322 323 324 325 326 327 328 329 382 383 922 923 928 929
-1B_ 330 331 332 333 334 335 336 337 338 339 392 393 932 933 938 939
-1C_ 340 341 342 343 344 345 346 347 348 349 384 385 942 943 388 389
-1D_ 350 351 352 353 354 355 356 357 358 359 394 395 952 953 398 399
-1E_ 360 361 362 363 364 365 366 367 368 369 386 387 962 963 (988) (989)
-1F_ 370 371 372 373 374 375 376 377 378 379 396 397 972 973 (998) (999)
-20_ 400 401 402 403 404 405 406 407 408 409 480 481 804 805 884 885
-21_ 410 411 412 413 414 415 416 417 418 419 490 491 814 815 894 895
-22_ 420 421 422 423 424 425 426 427 428 429 482 483 824 825 848 849
-23_ 430 431 432 433 434 435 436 437 438 439 492 493 834 835 858 859
-24_ 440 441 442 443 444 445 446 447 448 449 484 485 844 845 488 489
-25_ 450 451 452 453 454 455 456 457 458 459 494 495 854 855 498 499
-26_ 460 461 462 463 464 465 466 467 468 469 486 487 864 865 (888) (889)
-27_ 470 471 472 473 474 475 476 477 478 479 496 497 874 875 (898) (899)
-28_ 500 501 502 503 504 505 506 507 508 509 580 581 904 905 984 985
-29_ 510 511 512 513 514 515 516 517 518 519 590 591 914 915 994 995
-2A_ 520 521 522 523 524 525 526 527 528 529 582 583 924 925 948 949
-2B_ 530 531 532 533 534 535 536 537 538 539 592 593 934 935 958 959
-2C_ 540 541 542 543 544 545 546 547 548 549 584 585 944 945 588 589
-2D_ 550 551 552 553 554 555 556 557 558 559 594 595 954 955 598 599
-2E_ 560 561 562 563 564 565 566 567 568 569 586 587 964 965 (988) (989)
-2F_ 570 571 572 573 574 575 576 577 578 579 596 597 974 975 (998) (999)
-30_ 600 601 602 603 604 605 606 607 608 609 680 681 806 807 886 887
-31_ 610 611 612 613 614 615 616 617 618 619 690 691 816 817 896 897
-32_ 620 621 622 623 624 625 626 627 628 629 682 683 826 827 868 869
-33_ 630 631 632 633 634 635 636 637 638 639 692 693 836 837 878 879
-34_ 640 641 642 643 644 645 646 647 648 649 684 685 846 847 688 689
-35_ 650 651 652 653 654 655 656 657 658 659 694 695 856 857 698 699
-36_ 660 661 662 663 664 665 666 667 668 669 686 687 866 867 (888) (889)
-37_ 670 671 672 673 674 675 676 677 678 679 696 697 876 877 (898) (899)
-38_ 700 701 702 703 704 705 706 707 708 709 780 781 906 907 986 987
-39_ 710 711 712 713 714 715 716 717 718 719 790 791 916 917 996 997
-3A_ 720 721 722 723 724 725 726 727 728 729 782 783 926 927 968 969
-3B_ 730 731 732 733 734 735 736 737 738 739 792 793 936 937 978 979
-3C_ 740 741 742 743 744 745 746 747 748 749 784 785 946 947 788 789
-3D_ 750 751 752 753 754 755 756 757 758 759 794 795 956 957 798 799
-3E_ 760 761 762 763 764 765 766 767 768 769 786 787 966 967 (988) (989)
-3F_ 770 771 772 773 774 775 776 777 778 779 796 797 976 977 (998) (999)
-"""
-DPD_TO_BCD_PATTERN = (r"^([0-9A-F]{2})_\s+" + r"\s+".join([r"\(?(\d{3})\)?"] * 16) + r"$")
-DPD_TO_BCD_REGEX = re.compile(DPD_TO_BCD_PATTERN, re.M)
-
-
-def run_tst(generator, initial_regs, initial_sprs=None, svstate=0, mmu=False,
- initial_cr=0, mem=None,
- initial_fprs=None,
- pdecode2=None):
- if initial_sprs is None:
- initial_sprs = {}
- m = Module()
- comb = m.d.comb
- instruction = Signal(32)
-
- if pdecode2 is None:
- pdecode = create_pdecode(include_fp=initial_fprs is not None)
- pdecode2 = PowerDecode2(pdecode)
-
- gen = list(generator.generate_instructions())
- insncode = generator.assembly.splitlines()
- instructions = list(zip(gen, insncode))
-
- m.submodules.pdecode2 = pdecode2
- simulator = ISA(pdecode2, initial_regs, initial_sprs, initial_cr,
- initial_insns=gen, respect_pc=True,
- initial_svstate=svstate,
- initial_mem=mem,
- fpregfile=initial_fprs,
- disassembly=insncode,
- bigendian=0,
- mmu=mmu)
- comb += pdecode2.dec.raw_opcode_in.eq(instruction)
- sim = Simulator(m)
-
- def process():
-
- print ("GPRs")
- simulator.gpr.dump()
- print ("FPRs")
- simulator.fpr.dump()
-
- yield pdecode2.dec.bigendian.eq(0) # little / big?
- pc = simulator.pc.CIA.value
- index = pc//4
- while index < len(instructions):
- print("instr pc", pc)
- try:
- yield from simulator.setup_one()
- except KeyError: # indicates instruction not in imem: stop
- break
- yield Settle()
-
- ins, code = instructions[index]
- print(" 0x{:X}".format(ins & 0xffffffff))
- opname = code.split(' ')[0]
- print(code, opname)
-
- # ask the decoder to decode this binary data (endian'd)
- yield from simulator.execute_one()
- pc = simulator.pc.CIA.value
- index = pc//4
-
- sim.add_process(process)
- with sim.write_vcd("simulator.vcd", "simulator.gtkw",
- traces=[]):
- sim.run()
- return simulator
+def tstgen(mapping):
+ zeros = [0] * 32
+ length = len(mapping)
+ iregs_whole = list(mapping.keys())
+ oregs_whole = list(mapping.values())
+ for base in range(0, length, 32):
+ iregs = (iregs_whole[base:base + 32] + zeros)[:32]
+ oregs = (oregs_whole[base:base + 32] + zeros)[:32]
+ yield (iregs, oregs)
class BCDTestCase(FHDLTestCase):
pdecode = create_pdecode(include_fp=True)
self.pdecode2 = PowerDecode2(pdecode)
+ def run_tst(self, instr, mapping):
+ lst = [f"{instr} {reg}, {reg}" for reg in range(32)]
+ for (iregs, oregs) in tstgen(mapping):
+ with self.subTest():
+ with Program(lst, bigendian=False) as program:
+ sim = self.run_tst_program(program, iregs)
+ for gpr in range(32):
+ self.assertEqual(sim.gpr(gpr),
+ SelectableInt(oregs[gpr], 64))
+
def test_cdtbcd(self):
- # This test is a terrible slowpoke; let's check first 20 values
- # for now, and come up with some clever ideas on how to make
- # it run faster.
- initial_regs = [0] * 32
- for match in DPD_TO_BCD_REGEX.findall(DPD_TO_BCD_TABLE)[0:2]:
+ mapping = {}
+ for match in DPD_TO_BCD_REGEX.findall(DPD_TO_BCD_TABLE):
for digit in range(0x10):
- with self.subTest():
- dpd = int((match[0] + f"{digit:X}"), 16)
- bcd = ((int(match[1 + digit][0]) << 8) |
- (int(match[1 + digit][1]) << 4) |
- (int(match[1 + digit][2]) << 0))
- lst = ["cdtbcd 0, 1"]
- initial_regs[1] = dpd
- with Program(lst, bigendian=False) as program:
- sim = self.run_tst_program(program, initial_regs)
- self.assertEqual(sim.gpr(0), SelectableInt(bcd, 64))
+ dpd = int((match[0] + f"{digit:X}"), 16)
+ bcd = ((int(match[1 + digit][0]) << 8) |
+ (int(match[1 + digit][1]) << 4) |
+ (int(match[1 + digit][2]) << 0))
+ mapping[dpd] = bcd
+ self.run_tst("cdtbcd", mapping)
def test_cbcdtd(self):
- # This test is a terrible slowpoke; let's check first 20 values
- # for now, and come up with some clever ideas on how to make
- # it run faster.
- initial_regs = [0] * 32
- for match in BCD_TO_DPD_REGEX.findall(BCD_TO_DPD_TABLE)[0:2]:
+ mapping = {}
+ for match in BCD_TO_DPD_REGEX.findall(BCD_TO_DPD_TABLE):
for digit in range(10):
- with self.subTest():
- bcd = ((int(match[0][0]) << 8) |
- (int(match[0][1]) << 4) |
- (int(digit) << 0))
- dpd = int(match[1 + digit], 16)
- # TODO: append 32 instructions here
- # "cbcdtd %d %d" % (regnum, regnum)
- lst = ["cbcdtd 0, 1"]
- initial_regs[1] = bcd
- with Program(lst, bigendian=False) as program:
- sim = self.run_tst_program(program, initial_regs)
- self.assertEqual(sim.gpr(0), SelectableInt(dpd, 64))
+ bcd = ((int(match[0][0]) << 8) |
+ (int(match[0][1]) << 4) |
+ (int(digit) << 0))
+ dpd = int(match[1 + digit], 16)
+ mapping[bcd] = dpd
+ self.run_tst("cbcdtd", mapping)
+
+ def test_addg6s(self):
+ # Reference implementation for addg6s, adopted to Python.
+ # https://github.com/antonblanchard/microwatt/blob/master/execute1.vhdl
+ def addg6s(a, b):
+ def bits(value, bits):
+ lsb = [((value >> bit) & 1) for bit in range(bits, -1, -1)]
+ return list(reversed(lsb))
+
+ a_in = bits(a, 64)
+ b_in = bits(b, 64)
+ sum_with_carry = bits((a + b), 65)
+
+ addg6s = [0] * 64
+ for i in range(16):
+ lo = i * 4
+ hi = (i + 1) * 4
+ if (a_in[hi] ^ b_in[hi] ^ (sum_with_carry[hi] == 0)):
+ addg6s[lo:lo + 3 + 1] = [0, 1, 1, 0]
+ if sum_with_carry[64] == 0:
+ addg6s[60:63] = [0, 1, 1, 0]
+ return int("".join(map(str, reversed(addg6s))), 2)
+
+ bcd = [f"{digit:04b}" for digit in range(10)]
+ def rng10(): return random.randrange(0, 10)
+ def bcdrng(): return int("".join((bcd[rng10()] for _ in range(16))), 2)
+
+ lst = [f"addg6s {gpr}, {gpr + 0}, {gpr + 1}" for gpr in range(31)]
+ oregs = [0] * 32
+ for _ in range(16):
+ iregs = [bcdrng() for _ in range(32)]
+ for gpr in range(31):
+ oregs[gpr] = addg6s(iregs[gpr + 0], iregs[gpr + 1])
+ with self.subTest():
+ with Program(lst, bigendian=False) as program:
+ sim = self.run_tst_program(program, iregs)
+ for gpr in range(31):
+ self.assertEqual(sim.gpr(gpr),
+ SelectableInt(oregs[gpr], 64))
def run_tst_program(self, prog, initial_regs=[0] * 32):
simulator = run_tst(prog, initial_regs, pdecode2=self.pdecode2)
projects / openpower-isa.git / blobdiff