better ways to do sign-inversion (without multiply which rounds)

[openpower-isa.git] / src / openpower / decoder / isa / test_caller_fp.py

diff --git a/src/openpower/decoder/isa/test_caller_fp.py b/src/openpower/decoder/isa/test_caller_fp.py
index cc87701a0a0100c9398a754d67a1416db6c2e167..615ff5d5efda3b685487d3d603a2017b4d3bdbaf 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_fp.py
+++ b/src/openpower/decoder/isa/test_caller_fp.py
@@ -224,7 +224,7 @@ class DecoderTestCase(FHDLTestCase):
 
         with Program(lst, bigendian=False) as program:
             sim = self.run_tst_program(program, initial_fprs=fprs)
-            self.assertEqual(sim.fpr(3), SelectableInt(0x3d9d8b31c0000000, 64))
+            self.assertEqual(sim.fpr(3), SelectableInt(0x3d8b1663a0000000, 64))
 
     def test_fp_muls4(self):
         """>>> lst = ["fmuls 3, 1, 2",