FP mul test, correct pseudocode to use FRC

[openpower-isa.git] / src / openpower / decoder / isa / test_caller_fp.py

diff --git a/src/openpower/decoder/isa/test_caller_fp.py b/src/openpower/decoder/isa/test_caller_fp.py
index a0635fc12c92fea45c9ef03760b532e5a5015a99..c2cbd4ddb111fc51bf82d9e7ccfa849d3ba7c658 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_fp.py
+++ b/src/openpower/decoder/isa/test_caller_fp.py
@@ -178,6 +178,23 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.fpr(2), SelectableInt(0xC02399999999999A, 64))
             self.assertEqual(sim.fpr(3), SelectableInt(0xC006666666666668, 64))
 
+    def test_fp_mul(self):
+        """>>> lst = ["fmul 3, 1, 2",
+                     ]
+        """
+        lst = ["fmul 3, 1, 2", # 7.0 * -9.8 = -68.6
+                     ]
+
+        fprs = [0] * 32
+        fprs[1] = 0x401C000000000000  # 7.0
+        fprs[2] = 0xC02399999999999A  # -9.8
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, initial_fprs=fprs)
+            self.assertEqual(sim.fpr(1), SelectableInt(0x401C000000000000, 64))
+            self.assertEqual(sim.fpr(2), SelectableInt(0xC02399999999999A, 64))
+            self.assertEqual(sim.fpr(3), SelectableInt(0xC051266666666667, 64))
+
     def run_tst_program(self, prog, initial_regs=None,
                               initial_mem=None,
                               initial_fprs=None):