from openpower.decoder.selectable_int import SelectableInt
from openpower.decoder.orderedset import OrderedSet
from openpower.decoder.isa.all import ISA
+from openpower.consts import PIb
class Register:
def test_load_misalign(self):
lst = ["addi 2, 0, 0x0010", # get PC off of zero
- "ldx 3, 1, 0",
+ "ldx 3, 0, 1",
]
initial_regs = [0] * 32
- initial_regs[1] = 0xFFFFFFFFFFFFFFFF # deliberately misaligned
+ all1s = 0xFFFFFFFFFFFFFFFF
+ initial_regs[1] = all1s
initial_regs[2] = 0x0008
initial_mem = {0x0000: (0x5432123412345678, 8),
0x0008: (0xabcdef0187654321, 8),
with Program(lst, bigendian=False) as program:
sim = self.run_tst_program(program, initial_regs, initial_mem)
- self.assertEqual(sim.gpr(1), SelectableInt(-1, 64))
+ self.assertEqual(sim.gpr(1), SelectableInt(all1s, 64))
self.assertEqual(sim.gpr(3), SelectableInt(0, 64))
- self.assertEqual(sim.spr['DAR'], SelectableInt(-1, 64))
+ print ("DAR", hex(sim.spr['DAR'].value))
+ print ("PC", hex(sim.pc.CIA.value))
+ # TODO get MSR, test that.
+ # TODO, test rest of SRR1 equal to zero
+ self.assertEqual(sim.spr['SRR1'][PIb.PRIV], 0x1) # expect priv bit
+ self.assertEqual(sim.spr['SRR0'], 0x4) # expect to be 2nd op
+ self.assertEqual(sim.spr['DAR'], all1s) # expect failed LD addr
+ self.assertEqual(sim.pc.CIA.value, 0x600) # align exception
def run_tst_program(self, prog, initial_regs=[0] * 32, initial_mem=None):
simulator = run_tst(prog, initial_regs, mem=initial_mem)