from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
from nmutil.formaltest import FHDLTestCase
import unittest
from openpower.decoder.isa.caller import ISACaller
from openpower.consts import SVP64CROffs
from copy import deepcopy
+
class DecoderTestCase(FHDLTestCase):
def _check_regs(self, sim, expected):
self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
def test_sv_load_store(self):
- """>>> lst = ["addi 1, 0, 0x0010",
- "addi 2, 0, 0x0008",
- "addi 5, 0, 0x1234",
- "addi 6, 0, 0x1235",
- "sv.stw 5.v, 0(1.v)",
- "sv.lwz 9.v, 0(1.v)"]
+ """>>> lst = ["addi 16, 0, 0x0010",
+ "addi 17, 0, 0x0008",
+ "addi 4, 0, 0x1234",
+ "addi 5, 0, 0x1235",
+ "sv.stw *4, 0(*1)",
+ "sv.lwz *8, 0(*1)"]
"""
- lst = SVP64Asm(["addi 1, 0, 0x0010",
- "addi 2, 0, 0x0008",
- "addi 5, 0, 0x1234",
- "addi 6, 0, 0x1235",
- "sv.stw 5.v, 0(1.v)",
- "sv.lwz 9.v, 0(1.v)"])
+ lst = SVP64Asm(["addi 16, 0, 0x0010",
+ "addi 17, 0, 0x0008",
+ "addi 4, 0, 0x1234",
+ "addi 5, 0, 0x1235",
+ "sv.stw *4, 0(*16)",
+ "sv.lwz *8, 0(*16)"])
lst = list(lst)
# SVSTATE (in this case, VL=2)
svstate = SVP64State()
- svstate.vl[0:7] = 2 # VL
- svstate.maxvl[0:7] = 2 # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 2 # VL
+ svstate.maxvl = 2 # MAXVL
+ print ("SVSTATE", bin(svstate.asint()))
with Program(lst, bigendian=False) as program:
sim = self.run_tst_program(program, svstate=svstate)
print(sim.gpr(1))
- self.assertEqual(sim.gpr(9), SelectableInt(0x1234, 64))
- self.assertEqual(sim.gpr(10), SelectableInt(0x1235, 64))
+ self.assertEqual(sim.gpr(8), SelectableInt(0x1234, 64))
+ self.assertEqual(sim.gpr(9), SelectableInt(0x1235, 64))
def test_sv_add(self):
- """>>> lst = ['sv.add 1.v, 5.v, 9.v'
+ """>>> lst = ['sv.add *1, *5, *9'
]
adds:
* 1 = 5 + 9 => 0x5555 = 0x4321+0x1234
* 2 = 6 + 10 => 0x3334 = 0x2223+0x1111
"""
- isa = SVP64Asm(['sv.add 1.v, 5.v, 9.v'
+ isa = SVP64Asm(['sv.add *1, *5, *9'
])
lst = list(isa)
print ("listing", lst)
initial_regs[6] = 0x2223
# SVSTATE (in this case, VL=2)
svstate = SVP64State()
- svstate.vl[0:7] = 2 # VL
- svstate.maxvl[0:7] = 2 # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 2 # VL
+ svstate.maxvl = 2 # MAXVL
+ print ("SVSTATE", bin(svstate.asint()))
# copy before running, then compute answers
expected_regs = deepcopy(initial_regs)
expected_regs[1] = initial_regs[5] + initial_regs[9] # 0x5555
self._check_regs(sim, expected_regs)
def test_sv_add_2(self):
- """>>> lst = ['sv.add 1, 5.v, 9.v' ]
+ """>>> lst = ['sv.add 1, *5, *9' ]
adds:
* 1 = 5 + 9 => 0x5555 = 0x4321+0x1234
* r1 is scalar so ENDS EARLY
"""
- isa = SVP64Asm(['sv.add 1, 5.v, 9.v'
+ isa = SVP64Asm(['sv.add 1, *5, *9'
])
lst = list(isa)
print ("listing", lst)
initial_regs[6] = 0x2223
# SVSTATE (in this case, VL=2)
svstate = SVP64State()
- svstate.vl[0:7] = 2 # VL
- svstate.maxvl[0:7] = 2 # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 2 # VL
+ svstate.maxvl = 2 # MAXVL
+ print ("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[1] = initial_regs[5] + initial_regs[9] # 0x5555
self._check_regs(sim, expected_regs)
def test_sv_add_3(self):
- """>>> lst = ['sv.add 1.v, 5, 9.v' ]
+ """>>> lst = ['sv.add *1, 5, *9' ]
adds:
* 1 = 5 + 9 => 0x5555 = 0x4321+0x1234
* 2 = 5 + 10 => 0x5432 = 0x4321+0x1111
"""
- isa = SVP64Asm(['sv.add 1.v, 5, 9.v'
+ isa = SVP64Asm(['sv.add *1, 5, *9'
])
lst = list(isa)
print ("listing", lst)
initial_regs[6] = 0x2223
# SVSTATE (in this case, VL=2)
svstate = SVP64State()
- svstate.vl[0:7] = 2 # VL
- svstate.maxvl[0:7] = 2 # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 2 # VL
+ svstate.maxvl = 2 # MAXVL
+ print ("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[1] = initial_regs[5] + initial_regs[9] # 0x5555
self._check_regs(sim, expected_regs)
def test_sv_add_vl_0(self):
- """>>> lst = ['sv.add 1, 5.v, 9.v'
+ """>>> lst = ['sv.add 1, *5, *9'
]
adds:
* none because VL is zero
"""
- isa = SVP64Asm(['sv.add 1, 5.v, 9.v'
+ isa = SVP64Asm(['sv.add 1, *5, *9'
])
lst = list(isa)
print ("listing", lst)
initial_regs[6] = 0x2223
# SVSTATE (in this case, VL=0)
svstate = SVP64State()
- svstate.vl[0:7] = 0 # VL
- svstate.maxvl[0:7] = 0 # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 0 # VL
+ svstate.maxvl = 0 # MAXVL
+ print ("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
self._check_regs(sim, expected_regs)
def test_sv_add_cr(self):
- """>>> lst = ['sv.add. 1.v, 5.v, 9.v'
+ """>>> lst = ['sv.add. *1, *5, *9'
]
adds when Rc=1: TODO CRs higher up
* 1 = 5 + 9 => 0 = -1+1 CR0=0b100
* 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 CR1=0b010
"""
- isa = SVP64Asm(['sv.add. 1.v, 5.v, 9.v'
+ isa = SVP64Asm(['sv.add. *1, *5, *9'
])
lst = list(isa)
print ("listing", lst)
initial_regs[6] = 0x2223
# SVSTATE (in this case, VL=2)
svstate = SVP64State()
- svstate.vl[0:7] = 2 # VL
- svstate.maxvl[0:7] = 2 # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 2 # VL
+ svstate.maxvl = 2 # MAXVL
+ print ("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[1] = initial_regs[5] + initial_regs[9] # 0x0