whoops, no ability to add comments in between functions in pseudocode

[openpower-isa.git] / src / openpower / decoder / isa / test_caller_svp64.py

diff --git a/src/openpower/decoder/isa/test_caller_svp64.py b/src/openpower/decoder/isa/test_caller_svp64.py
index 7cc04f403c0e0632de42440960fe221b333aaa42..a8e94c333480f6d0c344efb61991e3efa762944b 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64.py
+++ b/src/openpower/decoder/isa/test_caller_svp64.py
@@ -2,19 +2,20 @@ from nmigen import Module, Signal
 from nmigen.back.pysim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
-from soc.decoder.isa.caller import ISACaller
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.simulator.program import Program
-from soc.decoder.isa.caller import ISACaller, SVP64State
-from soc.decoder.selectable_int import SelectableInt
-from soc.decoder.orderedset import OrderedSet
-from soc.decoder.isa.all import ISA
-from soc.decoder.isa.test_caller import Register, run_tst
-from soc.sv.trans.svp64 import SVP64Asm
-from soc.consts import SVP64CROffs
+from openpower.decoder.isa.caller import ISACaller
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.simulator.program import Program
+from openpower.decoder.isa.caller import ISACaller, SVP64State
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.decoder.orderedset import OrderedSet
+from openpower.decoder.isa.all import ISA
+from openpower.decoder.isa.test_caller import Register, run_tst
+from openpower.sv.trans.svp64 import SVP64Asm
+from openpower.consts import SVP64CROffs
 from copy import deepcopy
 
+
 class DecoderTestCase(FHDLTestCase):
 
     def _check_regs(self, sim, expected):
@@ -22,6 +23,13 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
 
     def test_sv_load_store(self):
+        """>>> lst = ["addi 1, 0, 0x0010",
+                        "addi 2, 0, 0x0008",
+                        "addi 5, 0, 0x1234",
+                        "addi 6, 0, 0x1235",
+                        "sv.stw 5.v, 0(1.v)",
+                        "sv.lwz 9.v, 0(1.v)"]
+        """
         lst = SVP64Asm(["addi 1, 0, 0x0010",
                         "addi 2, 0, 0x0008",
                         "addi 5, 0, 0x1234",
@@ -43,9 +51,12 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.gpr(10), SelectableInt(0x1235, 64))
 
     def test_sv_add(self):
-        # adds:
-        #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
-        #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
+        """>>> lst = ['sv.add 1.v, 5.v, 9.v'
+                       ]
+        adds:
+            * 1 = 5 + 9   => 0x5555 = 0x4321+0x1234
+            * 2 = 6 + 10  => 0x3334 = 0x2223+0x1111
+        """
         isa = SVP64Asm(['sv.add 1.v, 5.v, 9.v'
                        ])
         lst = list(isa)
@@ -72,9 +83,11 @@ class DecoderTestCase(FHDLTestCase):
             self._check_regs(sim, expected_regs)
 
     def test_sv_add_2(self):
-        # adds:
-        #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
-        #       r1 is scalar so ENDS EARLY
+        """>>> lst = ['sv.add 1, 5.v, 9.v' ]
+        adds:
+            * 1 = 5 + 9   => 0x5555 = 0x4321+0x1234
+            * r1 is scalar so ENDS EARLY
+        """
         isa = SVP64Asm(['sv.add 1, 5.v, 9.v'
                        ])
         lst = list(isa)
@@ -100,9 +113,12 @@ class DecoderTestCase(FHDLTestCase):
             self._check_regs(sim, expected_regs)
 
     def test_sv_add_3(self):
-        # adds:
-        #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
-        #       2 = 5 + 10  => 0x5432 = 0x4321+0x1111
+        """>>> lst = ['sv.add 1.v, 5, 9.v' ]
+
+        adds:
+            * 1 = 5 + 9   => 0x5555 = 0x4321+0x1234
+            * 2 = 5 + 10  => 0x5432 = 0x4321+0x1111
+        """
         isa = SVP64Asm(['sv.add 1.v, 5, 9.v'
                        ])
         lst = list(isa)
@@ -129,8 +145,11 @@ class DecoderTestCase(FHDLTestCase):
             self._check_regs(sim, expected_regs)
 
     def test_sv_add_vl_0(self):
-        # adds:
-        #       none because VL is zer0
+        """>>> lst = ['sv.add 1, 5.v, 9.v'
+                       ]
+        adds:
+            * none because VL is zero
+        """
         isa = SVP64Asm(['sv.add 1, 5.v, 9.v'
                        ])
         lst = list(isa)
@@ -155,9 +174,13 @@ class DecoderTestCase(FHDLTestCase):
             self._check_regs(sim, expected_regs)
 
     def test_sv_add_cr(self):
-        # adds when Rc=1:                               TODO CRs higher up
-        #       1 = 5 + 9   => 0 = -1+1                 CR0=0b100
-        #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111   CR1=0b010
+        """>>> lst = ['sv.add. 1.v, 5.v, 9.v'
+                       ]
+
+        adds when Rc=1:                               TODO CRs higher up
+            * 1 = 5 + 9   => 0 = -1+1                 CR0=0b100
+            * 2 = 6 + 10  => 0x3334 = 0x2223+0x1111   CR1=0b010
+        """
         isa = SVP64Asm(['sv.add. 1.v, 5.v, 9.v'
                        ])
         lst = list(isa)