move D-Immediate rewriting in ISACaller into separate function

[openpower-isa.git] / src / openpower / decoder / isa / test_caller_svp64_bc.py

diff --git a/src/openpower/decoder/isa/test_caller_svp64_bc.py b/src/openpower/decoder/isa/test_caller_svp64_bc.py
index 65ba1b70b72c862d5df0d346f25f5b26e83f7d9b..0dda9fb89150f3ee9b3ed5f0e3d0d1d559eab544 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_bc.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_bc.py
@@ -27,15 +27,15 @@ class DecoderTestCase(FHDLTestCase):
                         "addi 2, 0, 0x0008",
                         "addi 5, 0, 0x1234",
                         "addi 6, 0, 0x1235",
-                        "sv.stw 5.v, 0(1.v)",
-                        "sv.lwz 9.v, 0(1.v)"]
+                        "sv.stw *5, 0(*1)",
+                        "sv.lwz *9, 0(*1)"]
         """
         lst = SVP64Asm(["addi 1, 0, 0x0010",
                         "addi 2, 0, 0x0008",
                         "addi 5, 0, 0x1234",
                         "addi 6, 0, 0x1235",
-                        "sv.stw 5.v, 0(1.v)",
-                        "sv.lwz 9.v, 0(1.v)"])
+                        "sv.stw *5, 0(*1)",
+                        "sv.lwz *9, 0(*1)"])
         lst = list(lst)
 
         # SVSTATE (in this case, VL=2)
@@ -51,13 +51,13 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.gpr(10), SelectableInt(0x1235, 64))
 
     def test_sv_branch_cond(self):
-        for i in [0, 10]: #[0, 10]:
+        for i in [0, 10]: #, 10]: #[0, 10]:
             lst = SVP64Asm(
                 [f"addi 1, 0, {i}",  # set r1 to i
                  f"addi 2, 0, {i}",  # set r2 to i
                 "cmpi cr0, 1, 1, 10",  # compare r1 with 10 and store to cr0
                 "cmpi cr1, 1, 2, 10",  # compare r2 with 10 and store to cr1
-                "sv.bc 12, 2.v, 0x8",    # beq 0x8 -
+                "sv.bc 12, *2, 0xc",    # beq 0xc -
                                        # branch if r1 equals 10 to the nop below
                 "addi 3, 0, 0x1234",   # if r1 == 10 this shouldn't execute
                 "or 0, 0, 0"]          # branch target
@@ -77,15 +77,42 @@ class DecoderTestCase(FHDLTestCase):
                 else:
                     self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64))
 
+    def test_sv_branch_cond_all(self):
+        for i in [7, 8, 9]:
+            lst = SVP64Asm(
+                [f"addi 1, 0, {i+1}",  # set r1 to i
+                 f"addi 2, 0, {i}",  # set r2 to i
+                "cmpi cr0, 1, 1, 8",  # compare r1 with 10 and store to cr0
+                "cmpi cr1, 1, 2, 8",  # compare r2 with 10 and store to cr1
+                "sv.bc/all 12, *1, 0xc",    # bgt 0xc - branch if BOTH
+                                       # r1 AND r2 greater 8 to the nop below
+                "addi 3, 0, 0x1234",   # if tests fail this shouldn't execute
+                "or 0, 0, 0"]          # branch target
+                )
+            lst = list(lst)
+
+            # SVSTATE (in this case, VL=2)
+            svstate = SVP64State()
+            svstate.vl = 2 # VL
+            svstate.maxvl = 2 # MAXVL
+            print ("SVSTATE", bin(svstate.asint()))
+
+            with Program(lst, bigendian=False) as program:
+                sim = self.run_tst_program(program, svstate=svstate)
+                if i == 9:
+                    self.assertEqual(sim.gpr(3), SelectableInt(0, 64))
+                else:
+                    self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64))
+
     def tst_sv_add_cr(self):
-        """>>> lst = ['sv.add. 1.v, 5.v, 9.v'
+        """>>> lst = ['sv.add. *1, *5, *9'
                        ]
 
         adds when Rc=1:                               TODO CRs higher up
             * 1 = 5 + 9   => 0 = -1+1                 CR0=0b100
             * 2 = 6 + 10  => 0x3334 = 0x2223+0x1111   CR1=0b010
         """
-        isa = SVP64Asm(['sv.add. 1.v, 5.v, 9.v'
+        isa = SVP64Asm(['sv.add. *1, *5, *9'
                        ])
         lst = list(isa)
         print ("listing", lst)