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[openpower-isa.git] / src / openpower / decoder / isa / test_caller_svp64_chacha20.py

diff --git a/src/openpower/decoder/isa/test_caller_svp64_chacha20.py b/src/openpower/decoder/isa/test_caller_svp64_chacha20.py
index cde49cfb24ba592fc19d399f66958c0aca59fbef..caa98d32e28f79a3c997d87b385d38a03731598c 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_chacha20.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_chacha20.py
@@ -89,7 +89,8 @@ class SVSTATETestCase(FHDLTestCase):
         sim.gpr.dump()
         for i in range(32):
             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64),
-                             "GPR %d %x expected %x" % (i, sim.gpr(i).value, expected[i]))
+                             "GPR %d %x expected %x" % \
+                             (i, sim.gpr(i).value, expected[i]))
 
     def test_1_sv_chacha20_main_rounds(self):
         """chacha20 main rounds