have to now add LD/ST-update instructions to list of explicit-allowed

[openpower-isa.git] / src / openpower / decoder / isa / test_caller_svp64_dd_ffirst.py

diff --git a/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py b/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py
index 40e31b1c9a64d5abb92bdb527653ab95d686b235..c9e98e48478ececf463979f730c11a7765315664 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py
@@ -31,6 +31,7 @@ class DecoderTestCase(FHDLTestCase):
         vec = [9, 8, 3, 4]
 
         res = []
+        cr_res = []
         # store GPRs
         for i, x in enumerate(vec):
             gprs[i] = x
@@ -41,17 +42,28 @@ class DecoderTestCase(FHDLTestCase):
             for i in range(4):
                 val = sim.gpr(i).value
                 res.append(val)
+                cr_res.append(0)
                 print("i", i, val)
             # confirm that the results are as expected
             expected = deepcopy(vec)
             expected_vl = 0
             for i in range(4):
-                result = expected[i] - gprs[8]
-                expected[i] = result
+                # calculate expected result and expected CR field
+                result = vec[i] - gprs[8]
+                crf = ((result==0)<<1) | ((result > 0)<<2) | ((result < 0) << 3)
+                cr_res[i] = crf
                 if result <= 0:
                     break
+                # VLi=0 - test comes FIRST!
+                expected[i] = result
                 # only write out if successful
                 expected_vl += 1
+
+            for i, v in enumerate(cr_res):
+                crf = sim.crl[i].get_range().value
+                print ("crf", i, res[i], bin(crf), bin(v))
+                self.assertEqual(crf, v)
+
             for i, v in enumerate(res):
                 self.assertEqual(v, expected[i])
 
@@ -76,6 +88,7 @@ class DecoderTestCase(FHDLTestCase):
         vec = [9, 8, 3, 4]
 
         res = []
+        cr_res = []
         # store GPRs
         for i, x in enumerate(vec):
             gprs[i] = x
@@ -86,14 +99,23 @@ class DecoderTestCase(FHDLTestCase):
             for i in range(4):
                 val = sim.gpr(i).value
                 res.append(val)
+                cr_res.append(0)
                 print("i", i, val)
             # confirm that the results are as expected
             expected = deepcopy(vec)
             for i in range(4):
-                result = expected[i] - gprs[8]
-                expected[i] = result
+                result = vec[i] - gprs[8]
+                crf = ((result==0)<<1) | ((result > 0)<<2) | ((result < 0) << 3)
+                cr_res[i] = crf
                 if result == 0:
                     break
+                # VLi=0 - test comes FIRST!
+                expected[i] = result
+            for i, v in enumerate(cr_res):
+                crf = sim.crl[i].get_range().value
+                print ("crf", i, res[i], bin(crf), bin(v))
+                self.assertEqual(crf, v)
+
             for i, v in enumerate(res):
                 self.assertEqual(v, expected[i])
 
@@ -133,9 +155,10 @@ class DecoderTestCase(FHDLTestCase):
             expected = deepcopy(vec)
             for i in range(4):
                 result = expected[i] - gprs[8]
-                expected[i] = result
                 if result == 0:
                     break
+                # VLi=0 - test comes FIRST!
+                expected[i] = result
             for i, v in enumerate(res):
                 self.assertEqual(v, expected[i])
 
@@ -145,6 +168,8 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.svstate.dststep, 0)
 
     def test_sv_addi_ffirst_vli(self):
+        """data-dependent fail-first with VLi=1, the test comes *after* write
+        """
         lst = SVP64Asm(["sv.subf/ff=RC1/vli *0,8,*0"
                         ])
         lst = list(lst)
@@ -174,6 +199,7 @@ class DecoderTestCase(FHDLTestCase):
             # confirm that the results are as expected
             expected = deepcopy(vec)
             for i in range(4):
+                # VLi=1 - test comes AFTER write!
                 expected[i] -= gprs[8]
                 if expected[i] == 0:
                     break