add (untested) TestRunner based on soc test_runner.py

[openpower-isa.git] / src / openpower / decoder / isa / test_caller_svp64_fft.py

diff --git a/src/openpower/decoder/isa/test_caller_svp64_fft.py b/src/openpower/decoder/isa/test_caller_svp64_fft.py
index 4febee386b4f54fe20635199c638ae417ead217c..25970efdf44c398bf262b3c80210b2057ae683d0 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_fft.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_fft.py
@@ -200,7 +200,7 @@ class FFTTestCase(FHDLTestCase):
                              "svremap 31, 1, 0, 2, 0, 1, 0",
                             "sv.ffmadds 0.v, 0.v, 0.v, 8.v",
                             "setvl. 0, 0, 1, 1, 0, 0",
-                            "bc 4, 2, -16"
+                            "bc 6, 3, -16"
                             ])
             runs a full in-place O(N log2 N) butterfly schedule for
             Discrete Fourier Transform.  this version however uses
@@ -215,7 +215,7 @@ class FFTTestCase(FHDLTestCase):
                          "svremap 31, 1, 0, 2, 0, 1, 0",
                         "sv.ffmadds 0.v, 0.v, 0.v, 8.v",
                         "setvl. 0, 0, 1, 1, 0, 0",
-                        "bc 4, 2, -16"
+                        "bc 6, 3, -16"
                         ])
         lst = list(lst)
 
@@ -287,7 +287,7 @@ class FFTTestCase(FHDLTestCase):
                          "svremap 26, 0, 0, 0, 0, 1, 1",
                         "sv.ffadds 0.v, 24, 0.v",
                         "setvl. 0, 0, 1, 1, 0, 0",
-                        "bc 4, 2, -28"
+                        "bc 6, 3, -28"
                             ])
 
             runs a full in-place O(N log2 N) butterfly schedule for
@@ -326,7 +326,7 @@ class FFTTestCase(FHDLTestCase):
                          "svremap 26, 0, 0, 0, 0, 1, 0",
                         "sv.ffadds 0.v, 24, 0.v",
                         "setvl. 0, 0, 1, 1, 0, 0",
-                        "bc 4, 2, -28"
+                        "bc 6, 3, -28"
                         ])
         lst = list(lst)
 
@@ -530,10 +530,16 @@ class FFTTestCase(FHDLTestCase):
 
             however it turns out that they can be *merged*, and for
             the first one (sv.fmadds/sv.fmsubs) the scalar arguments (RT, RB)
-            *ignore* their REMAPs (by definition), and for the second
-            one (sv.ffads) exactly the right REMAPs are also ignored!
+            *ignore* their REMAPs (by definition, because you can't REMAP
+            scalar operands), and for the second one (sv.ffads) exactly the
+            right REMAPs are also ignored!
 
+            therefore we can merge:
+                "svremap 5, 1, 0, 2, 0, 0, 1",
+                "svremap 26, 0, 0, 0, 0, 1, 1",
+            into:
                 "svremap 31, 1, 0, 2, 0, 1, 1",
+            and save one instruction.
         """
         lst = SVP64Asm( [
                         # set triple butterfly mode with persistent "REMAP"
@@ -554,7 +560,7 @@ class FFTTestCase(FHDLTestCase):
 
                         # svstep loop
                         "setvl. 0, 0, 1, 1, 0, 0",
-                        "bc 4, 2, -56"
+                        "bc 6, 3, -56"
                         ])
         lst = list(lst)
 
@@ -681,15 +687,18 @@ class FFTTestCase(FHDLTestCase):
                 self.assertEqual(sim.fpr(i+6), u)
 
     def test_sv_remap_fpmadds_fft_ldst(self):
-        """>>> lst = ["svshape 8, 1, 1, 1, 0",
-                     "svremap 31, 1, 0, 2, 0, 1, 0",
-                      "sv.ffmadds 2.v, 2.v, 2.v, 10.v"
-                     ]
+        """>>>lst = ["setvl 0, 0, 8, 0, 1, 1",
+                         "sv.lfssh 0.v, 4(0), 20", # bit-reversed
+                         "svshape 8, 1, 1, 1, 0",
+                         "svremap 31, 1, 0, 2, 0, 1, 0",
+                         "sv.ffmadds 0.v, 0.v, 0.v, 8.v"
+
             runs a full in-place O(N log2 N) butterfly schedule for
             Discrete Fourier Transform, using bit-reversed LD/ST
         """
-        lst = SVP64Asm( ["setvl 0, 0, 8, 0, 1, 1",
-                         "sv.lfsbr 0.v, 4(0), 20", # bit-reversed
+        lst = SVP64Asm( ["svshape 8, 1, 1, 15, 0",
+                         "svremap 1, 0, 0, 0, 0, 0, 0, 0",
+                         "sv.lfssh 0.v, 4(0), 20", # shifted
                          "svshape 8, 1, 1, 1, 0",
                          "svremap 31, 1, 0, 2, 0, 1, 0",
                          "sv.ffmadds 0.v, 0.v, 0.v, 8.v"
@@ -730,7 +739,8 @@ class FFTTestCase(FHDLTestCase):
             print ("mem dump")
             print (sim.mem.dump())
 
-            # work out the results with the twin mul/add-sub
+            # work out the results with the twin mul/add-sub,
+            # note bit-reverse mode requested
             res = transform_radix2(av, coe, reverse=True)
 
             for i, expected in enumerate(res):