whoops, no ability to add comments in between functions in pseudocode

[openpower-isa.git] / src / openpower / decoder / isa / test_caller_svp64_fft.py

diff --git a/src/openpower/decoder/isa/test_caller_svp64_fft.py b/src/openpower/decoder/isa/test_caller_svp64_fft.py
index ae71a4496655b1b6f6086e9ecbf63bdd7e153118..28aca452946edbbca95e372e26be3b4d8626ff03 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_fft.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_fft.py
@@ -9,7 +9,7 @@ from openpower.decoder.selectable_int import SelectableInt
 from openpower.decoder.isa.test_caller import run_tst
 from openpower.sv.trans.svp64 import SVP64Asm
 from copy import deepcopy
-from openpower.decoder.helpers import fp64toselectable
+from openpower.decoder.helpers import fp64toselectable, SINGLE
 from openpower.decoder.isafunctions.double2single import DOUBLE2SINGLE
 
 
@@ -200,7 +200,7 @@ class FFTTestCase(FHDLTestCase):
                              "svremap 31, 1, 0, 2, 0, 1, 0",
                             "sv.ffmadds 0.v, 0.v, 0.v, 8.v",
                             "setvl. 0, 0, 1, 1, 0, 0",
-                            "bc 4, 2, -16"
+                            "bc 6, 3, -16"
                             ])
             runs a full in-place O(N log2 N) butterfly schedule for
             Discrete Fourier Transform.  this version however uses
@@ -215,7 +215,7 @@ class FFTTestCase(FHDLTestCase):
                          "svremap 31, 1, 0, 2, 0, 1, 0",
                         "sv.ffmadds 0.v, 0.v, 0.v, 8.v",
                         "setvl. 0, 0, 1, 1, 0, 0",
-                        "bc 4, 2, -16"
+                        "bc 6, 3, -16"
                         ])
         lst = list(lst)
 
@@ -287,7 +287,7 @@ class FFTTestCase(FHDLTestCase):
                          "svremap 26, 0, 0, 0, 0, 1, 1",
                         "sv.ffadds 0.v, 24, 0.v",
                         "setvl. 0, 0, 1, 1, 0, 0",
-                        "bc 4, 2, -28"
+                        "bc 6, 3, -28"
                             ])
 
             runs a full in-place O(N log2 N) butterfly schedule for
@@ -326,7 +326,7 @@ class FFTTestCase(FHDLTestCase):
                          "svremap 26, 0, 0, 0, 0, 1, 0",
                         "sv.ffadds 0.v, 24, 0.v",
                         "setvl. 0, 0, 1, 1, 0, 0",
-                        "bc 4, 2, -28"
+                        "bc 6, 3, -28"
                         ])
         lst = list(lst)
 
@@ -554,7 +554,7 @@ class FFTTestCase(FHDLTestCase):
 
                         # svstep loop
                         "setvl. 0, 0, 1, 1, 0, 0",
-                        "bc 4, 2, -56"
+                        "bc 6, 3, -56"
                         ])
         lst = list(lst)
 
@@ -681,18 +681,20 @@ class FFTTestCase(FHDLTestCase):
                 self.assertEqual(sim.fpr(i+6), u)
 
     def test_sv_remap_fpmadds_fft_ldst(self):
-        """>>> lst = ["svshape 8, 1, 1, 1, 0",
-                     "svremap 31, 1, 0, 2, 0, 1, 0",
-                      "sv.ffmadds 2.v, 2.v, 2.v, 10.v"
-                     ]
+        """>>>lst = ["setvl 0, 0, 8, 0, 1, 1",
+                         "sv.lfsbr 0.v, 4(0), 20", # bit-reversed
+                         "svshape 8, 1, 1, 1, 0",
+                         "svremap 31, 1, 0, 2, 0, 1, 0",
+                         "sv.ffmadds 0.v, 0.v, 0.v, 8.v"
+
             runs a full in-place O(N log2 N) butterfly schedule for
             Discrete Fourier Transform, using bit-reversed LD/ST
         """
         lst = SVP64Asm( ["setvl 0, 0, 8, 0, 1, 1",
                          "sv.lfsbr 0.v, 4(0), 20", # bit-reversed
-                         #"svshape 8, 1, 1, 1, 0",
-                         #"svremap 31, 1, 0, 2, 0, 1, 0",
-                         #"sv.ffmadds 0.v, 0.v, 0.v, 8.v"
+                         "svshape 8, 1, 1, 1, 0",
+                         "svremap 31, 1, 0, 2, 0, 1, 0",
+                         "sv.ffmadds 0.v, 0.v, 0.v, 8.v"
                         ])
         lst = list(lst)
 
@@ -707,12 +709,14 @@ class FFTTestCase(FHDLTestCase):
             fprs[i+8] = fp64toselectable(c)
         # store in memory
         mem = {}
+        val = 0
         for i, a in enumerate(av):
+            a = SINGLE(fp64toselectable(a)).value
             shift = (i % 2) == 1
             if shift == 0:
-                mem[(i//2)*8] = fp64toselectable(a).value
+                val = a
             else:
-                mem[(i//2)*8] |= fp64toselectable(a).value << 32
+                mem[(i//2)*8] = val | (a << 32)
 
         with Program(lst, bigendian=False) as program:
             sim = self.run_tst_program(program, initial_mem=mem,
@@ -728,8 +732,9 @@ class FFTTestCase(FHDLTestCase):
             print ("mem dump")
             print (sim.mem.dump())
 
-            # work out the results with the twin mul/add-sub
-            res = transform_radix2(av, coe)
+            # work out the results with the twin mul/add-sub,
+            # note bit-reverse mode requested
+            res = transform_radix2(av, coe, reverse=True)
 
             for i, expected in enumerate(res):
                 print ("i", i, float(sim.fpr(i)), "expected", expected)
@@ -742,7 +747,7 @@ class FFTTestCase(FHDLTestCase):
                 # reason: we are comparing FMAC against FMUL-plus-FADD-or-FSUB
                 # and the rounding is different
                 err = abs(actual - expected) / expected
-                self.assertTrue(err < 1e-7)
+                self.assertTrue(err < 1e-6)
 
     def run_tst_program(self, prog, initial_regs=None,
                               svstate=None,