from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
from nmutil.formaltest import FHDLTestCase
import unittest
from openpower.decoder.isa.caller import ISACaller
self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
def test_sv_fpload(self):
- """>>> lst = ["sv.lfsx 2.v, 0, 0.v"
+ """>>> lst = ["sv.lfsx *2, 0, *0"
]
"""
- lst = SVP64Asm(["sv.lfsx 2.v, 0, 0.v"
+ lst = SVP64Asm(["sv.lfsx *2, 0, *0"
])
lst = list(lst)
# SVSTATE (in this case, VL=2)
svstate = SVP64State()
- svstate.vl[0:7] = 2 # VL
- svstate.maxvl[0:7] = 2 # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 2 # VL
+ svstate.maxvl = 2 # MAXVL
+ print ("SVSTATE", bin(svstate.asint()))
# memory addresses 0x0000 and 0x0008
initial_mem = {0x0000: (0x42013333, 8), # 32.3
self.assertEqual(sim.fpr(3), SelectableInt(0xC004000000000000, 64))
def test_fp_single_ldst(self):
- """>>> lst = ["sv.lfsx 0.v, 0, 4.v", # load fp 1/2 from mem 0/8
- "sv.stfsu 0.v, 16(4.v)", # store fp 1/2, update RA *twice*
- "sv.lfs 3.v, 0(4.v)", # re-load from UPDATED r4/r5
+ """>>> lst = ["sv.lfsx *0, 0, *4", # load fp 1/2 from mem 0/8
+ "sv.stfsu *0, 16(*4)", # store fp 1/2, update RA *twice*
+ "sv.lfs *2, 0(*4)", # re-load from UPDATED r4/r5
]
This is quite an involved (deceptively simple looking) test.
Walkthrough:
- 1) sv.lfsx 0.v, 0, 4.v VL=2 so there are *two* lfsx operations
+ 1) sv.lfsx *0, 0, *4 VL=2 so there are *two* lfsx operations
lfsx 0, 0, 4 loads from MEM[GPR(4)], stores in FPR(0)
lfsx 1, 0, 5 loads from MEM[GPR(5)], stores in FPR(1)
- 2) sv.stfsu 0.v, 16(4.v) again, VL=2 so there are two ST-FP-update ops
+ 2) sv.stfsu *0, 16(*4) again, VL=2 so there are two ST-FP-update ops
stfsu 0, 16(4) EA=GPR(4)+16, FPR(0) to MEM[EA], EA to GPR(4)
stfsu 1, 16(5) EA=GPR(5)+16, FPR(0) to MEM[EA], EA to GPR(5)
writes of the calculated Effective Address to GPR, in regs 4 and 5
GPRs 4 and 5 are *overwritten*.
- 3) sv.lfs 3.v, 0(4.v) VL=2, so two immediate-LDs
+ 3) sv.lfs *3, 0(*4) VL=2, so two immediate-LDs
lfs 3, 0(4) EA=GPR(4)+0, FPR(3) = MEM[EA]
lfs 4, 0(5) EA=GPR(5)+0, FPR(4) = MEM[EA]
of the memory locations 0x10 and 0x18, which should contain the
single-precision FP numbers in the bottom 4 bytes. TODO
"""
- lst = SVP64Asm(["sv.lfsx 0.v, 0, 4.v",
- "sv.stfsu 0.v, 16(4.v)",
- "sv.lfs 3.v, 0(4.v)",
+ lst = SVP64Asm(["sv.lfsx *0, 0, *4",
+ "sv.stfsu *0, 16(*4)",
+ "sv.lfs *2, 0(*4)",
])
lst = list(lst)
# SVSTATE (in this case, VL=2)
svstate = SVP64State()
- svstate.vl[0:7] = 2 # VL
- svstate.maxvl[0:7] = 2 # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 2 # VL
+ svstate.maxvl = 2 # MAXVL
+ print ("SVSTATE", bin(svstate.asint()))
# memory addresses 0x0000 and 0x0008
initial_mem = {0x0000: (0x42013333, 8), # 32.3
self.assertEqual(sim.gpr(5), SelectableInt(0x18, 64))
self.assertEqual(sim.fpr(0), SelectableInt(0x4040266660000000, 64))
self.assertEqual(sim.fpr(1), SelectableInt(0xC004000000000000, 64))
- self.assertEqual(sim.fpr(3), SelectableInt(0x4040266660000000, 64))
- self.assertEqual(sim.fpr(4), SelectableInt(0xC004000000000000, 64))
+ self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64))
+ self.assertEqual(sim.fpr(3), SelectableInt(0xC004000000000000, 64))
def test_sv_fpadd(self):
- """>>> lst = ["sv.fadds 6.v, 2.v, 4.v"
+ """>>> lst = ["sv.fadds *6, *2, *4"
]
"""
- lst = SVP64Asm(["sv.fadds 6.v, 2.v, 4.v"
+ lst = SVP64Asm(["sv.fadds *6, *2, *4"
])
lst = list(lst)
# SVSTATE (in this case, VL=2)
svstate = SVP64State()
- svstate.vl[0:7] = 2 # VL
- svstate.maxvl[0:7] = 2 # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 2 # VL
+ svstate.maxvl = 2 # MAXVL
+ print ("SVSTATE", bin(svstate.asint()))
with Program(lst, bigendian=False) as program:
sim = self.run_tst_program(program, svstate=svstate,
self.assertEqual(sim.fpr(7), SelectableInt(0xc050266660000000, 64))
def test_sv_fpmadds(self):
- """>>> lst = ["sv.fmadds 6.v, 2.v, 4.v, 8"
+ """>>> lst = ["sv.fmadds *6, *2, *4, 8"
]
two vector mul-adds with a scalar in f8
* fp6 = fp2 * fp4 + f8 = 7.0 * 2.0 - 2.0 = 12.0
* fp7 = fp3 * fp5 + f8 = 7.0 * 2.0 - 2.0 = 12.0
"""
- lst = SVP64Asm(["sv.fmadds 6.v, 2.v, 4.v, 8"
+ lst = SVP64Asm(["sv.fmadds *6, *2, *4, 8"
])
lst = list(lst)
# SVSTATE (in this case, VL=2)
svstate = SVP64State()
- svstate.vl[0:7] = 2 # VL
- svstate.maxvl[0:7] = 2 # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 2 # VL
+ svstate.maxvl = 2 # MAXVL
+ print ("SVSTATE", bin(svstate.asint()))
with Program(lst, bigendian=False) as program:
sim = self.run_tst_program(program, svstate=svstate,