swap complicated bits, simplify ISACaller, reduce indent level

[openpower-isa.git] / src / openpower / decoder / isa / test_caller_svp64_fp.py

diff --git a/src/openpower/decoder/isa/test_caller_svp64_fp.py b/src/openpower/decoder/isa/test_caller_svp64_fp.py
index 7dda55a47360cc2069957f77457feb3dd07ee6bf..610fb59fabf71e20efd0559c39cb5e5bed3c8787 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_fp.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_fp.py
@@ -1,5 +1,5 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
 from openpower.decoder.isa.caller import ISACaller