add gpr lookup in Indexed SVSHAPE iterator (no elwidths yet)

[openpower-isa.git] / src / openpower / decoder / isa / test_caller_svp64_mapreduce.py

diff --git a/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py b/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py
index c30e41be4c1dc8c01b013b161bb582c2c9d8bb00..5fd6968ae2d2df3a6762581822b232baf49b4c99 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py
@@ -23,7 +23,7 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
 
     def test_sv_add_scalar_reduce(self):
-        """>>> lst = ['sv.add/mr 1, 5.v, 1'
+        """>>> lst = ['sv.add/mr 1, *5, 1'
                        ]
         note: there are 2 adds (VL=2) but *three values involved*
         adds:
@@ -31,7 +31,7 @@ class DecoderTestCase(FHDLTestCase):
             * 1 = 5 + 1  => 0x101 + 0x202 => 0x303
             * 1 = 6 + 1  => 0x303 + 0x404 => 0x707
         """
-        isa = SVP64Asm(['sv.add/mr 1, 5.v, 1'
+        isa = SVP64Asm(['sv.add/mr 1, *5, 1'
                        ])
         lst = list(isa)
         print ("listing", lst)
@@ -43,9 +43,9 @@ class DecoderTestCase(FHDLTestCase):
         initial_regs[6] = 0x0404
         # SVSTATE (in this case, VL=2)
         svstate = SVP64State()
-        svstate.vl[0:7] = 2 # VL
-        svstate.maxvl[0:7] = 2 # MAXVL
-        print ("SVSTATE", bin(svstate.spr.asint()))
+        svstate.vl = 2 # VL
+        svstate.maxvl = 2 # MAXVL
+        print ("SVSTATE", bin(svstate.asint()))
         # copy before running, then compute answers
         expected_regs = deepcopy(initial_regs)
         # r1 = r1 + r5 + r6
@@ -58,7 +58,7 @@ class DecoderTestCase(FHDLTestCase):
             self._check_regs(sim, expected_regs)
 
     def test_sv_add_prefix_sum(self):
-        """>>> lst = ['sv.add/mr 2.v, 2.v, 1.v'
+        """>>> lst = ['sv.add/mr *2, *2, *1'
                        ]
             adds performed - not in reverse
             * 2 = 2 + 1  => 1 + 2  =>  3
@@ -67,7 +67,7 @@ class DecoderTestCase(FHDLTestCase):
 
             pascal's triangle!
         """
-        isa = SVP64Asm(['sv.add/mr 2.v, 2.v, 1.v'
+        isa = SVP64Asm(['sv.add/mr *2, *2, *1'
                        ])
         lst = list(isa)
         print ("listing", lst)
@@ -80,9 +80,9 @@ class DecoderTestCase(FHDLTestCase):
         initial_regs[4] = 0x4
         # SVSTATE (in this case, VL=2)
         svstate = SVP64State()
-        svstate.vl[0:7] = 3 # VL
-        svstate.maxvl[0:7] = 3 # MAXVL
-        print ("SVSTATE", bin(svstate.spr.asint()))
+        svstate.vl = 3 # VL
+        svstate.maxvl = 3 # MAXVL
+        print ("SVSTATE", bin(svstate.asint()))
         # copy before running, then compute answers
         expected_regs = deepcopy(initial_regs)
         for i in range(3):
@@ -97,14 +97,14 @@ class DecoderTestCase(FHDLTestCase):
             self._check_regs(sim, expected_regs)
 
     def test_sv_add_prefix_sum_reverse(self):
-        """>>> lst = ['sv.add/mrr 2.v, 2.v, 1.v'
+        """>>> lst = ['sv.add/mrr *2, *2, *1'
                        ]
             adds performed - *in reverse order*
             * 4 = 4 + 3  => 1 + 2  =>  3
             * 3 = 3 + 2  => 3 + 2  =>  5
             * 2 = 2 + 1  => 3 + 4  =>  7
         """
-        isa = SVP64Asm(['sv.add/mrr 2.v, 2.v, 1.v'
+        isa = SVP64Asm(['sv.add/mrr *2, *2, *1'
                        ])
         lst = list(isa)
         print ("listing", lst)
@@ -117,9 +117,9 @@ class DecoderTestCase(FHDLTestCase):
         initial_regs[4] = 0x1
         # SVSTATE (in this case, VL=2)
         svstate = SVP64State()
-        svstate.vl[0:7] = 3 # VL
-        svstate.maxvl[0:7] = 3 # MAXVL
-        print ("SVSTATE", bin(svstate.spr.asint()))
+        svstate.vl = 3 # VL
+        svstate.maxvl = 3 # MAXVL
+        print ("SVSTATE", bin(svstate.asint()))
         # copy before running, then compute answers
         expected_regs = deepcopy(initial_regs)
         for i in range(3):
@@ -135,7 +135,7 @@ class DecoderTestCase(FHDLTestCase):
             self._check_regs(sim, expected_regs)
 
     def test_fp_muls_reduce(self):
-        """>>> lst = ["sv.fmuls/mr 1, 2.v, 1",
+        """>>> lst = ["sv.fmuls/mr 1, *2, 1",
                      ]
         note that VL=3 but *four values are involved*
         answer should be 7.0 * -9.8 * -9.8 * 2.0 = 1344.56
@@ -145,7 +145,7 @@ class DecoderTestCase(FHDLTestCase):
         * FPR 1 multiplied by FPR 3, -9.8
         * FPR 1 multiplied by FPR 4, 2.0
         """
-        isa = SVP64Asm(["sv.fmuls/mr 1, 2.v, 1",
+        isa = SVP64Asm(["sv.fmuls/mr 1, *2, 1",
                      ])
         lst = list(isa)
         print ("listing", lst)
@@ -158,9 +158,9 @@ class DecoderTestCase(FHDLTestCase):
 
         # SVSTATE (in this case, VL=2)
         svstate = SVP64State()
-        svstate.vl[0:7] = 3 # VL
-        svstate.maxvl[0:7] = 3 # MAXVL
-        print ("SVSTATE", bin(svstate.spr.asint()))
+        svstate.vl = 3 # VL
+        svstate.maxvl = 3 # MAXVL
+        print ("SVSTATE", bin(svstate.asint()))
 
         with Program(lst, bigendian=False) as program:
             sim = self.run_tst_program(program, svstate=svstate,
@@ -173,11 +173,11 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.fpr(4), SelectableInt(0x4000000000000000, 64))
 
     def test_sv_fpmadds(self):
-        """>>> lst = ["sv.fmadds/mr 6, 2.v, 4.v, 6"
+        """>>> lst = ["sv.fmadds/mr 6, *2, *4, 6"
                         ]
                 this example uses f6 as a multiply-accumulate-sum mapreduce
         """
-        lst = SVP64Asm(["sv.fmadds/mr 6, 2.v, 4.v, 6"
+        lst = SVP64Asm(["sv.fmadds/mr 6, *2, *4, 6"
                         ])
         lst = list(lst)
 
@@ -190,9 +190,9 @@ class DecoderTestCase(FHDLTestCase):
 
         # SVSTATE (in this case, VL=2)
         svstate = SVP64State()
-        svstate.vl[0:7] = 2 # VL
-        svstate.maxvl[0:7] = 2 # MAXVL
-        print ("SVSTATE", bin(svstate.spr.asint()))
+        svstate.vl = 2 # VL
+        svstate.maxvl = 2 # MAXVL
+        print ("SVSTATE", bin(svstate.asint()))
 
         with Program(lst, bigendian=False) as program:
             sim = self.run_tst_program(program, svstate=svstate,