whoops, no ability to add comments in between functions in pseudocode

[openpower-isa.git] / src / openpower / decoder / isa / test_caller_svp64_mapreduce.py

diff --git a/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py b/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py
index c5b57877eb941160aeb21fd6491a528e5c6da563..76094678b8e0fc764694418e89638fc4926a690d 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py
@@ -43,9 +43,9 @@ class DecoderTestCase(FHDLTestCase):
         initial_regs[6] = 0x0404
         # SVSTATE (in this case, VL=2)
         svstate = SVP64State()
-        svstate.vl[0:7] = 2 # VL
-        svstate.maxvl[0:7] = 2 # MAXVL
-        print ("SVSTATE", bin(svstate.spr.asint()))
+        svstate.vl = 2 # VL
+        svstate.maxvl = 2 # MAXVL
+        print ("SVSTATE", bin(svstate.asint()))
         # copy before running, then compute answers
         expected_regs = deepcopy(initial_regs)
         # r1 = r1 + r5 + r6
@@ -80,9 +80,9 @@ class DecoderTestCase(FHDLTestCase):
         initial_regs[4] = 0x4
         # SVSTATE (in this case, VL=2)
         svstate = SVP64State()
-        svstate.vl[0:7] = 3 # VL
-        svstate.maxvl[0:7] = 3 # MAXVL
-        print ("SVSTATE", bin(svstate.spr.asint()))
+        svstate.vl = 3 # VL
+        svstate.maxvl = 3 # MAXVL
+        print ("SVSTATE", bin(svstate.asint()))
         # copy before running, then compute answers
         expected_regs = deepcopy(initial_regs)
         for i in range(3):
@@ -117,9 +117,9 @@ class DecoderTestCase(FHDLTestCase):
         initial_regs[4] = 0x1
         # SVSTATE (in this case, VL=2)
         svstate = SVP64State()
-        svstate.vl[0:7] = 3 # VL
-        svstate.maxvl[0:7] = 3 # MAXVL
-        print ("SVSTATE", bin(svstate.spr.asint()))
+        svstate.vl = 3 # VL
+        svstate.maxvl = 3 # MAXVL
+        print ("SVSTATE", bin(svstate.asint()))
         # copy before running, then compute answers
         expected_regs = deepcopy(initial_regs)
         for i in range(3):
@@ -158,15 +158,15 @@ class DecoderTestCase(FHDLTestCase):
 
         # SVSTATE (in this case, VL=2)
         svstate = SVP64State()
-        svstate.vl[0:7] = 3 # VL
-        svstate.maxvl[0:7] = 3 # MAXVL
-        print ("SVSTATE", bin(svstate.spr.asint()))
+        svstate.vl = 3 # VL
+        svstate.maxvl = 3 # MAXVL
+        print ("SVSTATE", bin(svstate.asint()))
 
         with Program(lst, bigendian=False) as program:
             sim = self.run_tst_program(program, svstate=svstate,
                                                 initial_fprs=fprs)
             # answer should be 7.0 * -9.8 * -9.8 * 2.0 = 1344.56
-            self.assertEqual(sim.fpr(1), SelectableInt(0x4095023d60000000, 64))
+            self.assertEqual(sim.fpr(1), SelectableInt(0x4095023d20000000, 64))
             # these should not have been changed
             self.assertEqual(sim.fpr(2), SelectableInt(0xC02399999999999A, 64))
             self.assertEqual(sim.fpr(3), SelectableInt(0xC02399999999999A, 64))
@@ -190,9 +190,9 @@ class DecoderTestCase(FHDLTestCase):
 
         # SVSTATE (in this case, VL=2)
         svstate = SVP64State()
-        svstate.vl[0:7] = 2 # VL
-        svstate.maxvl[0:7] = 2 # MAXVL
-        print ("SVSTATE", bin(svstate.spr.asint()))
+        svstate.vl = 2 # VL
+        svstate.maxvl = 2 # MAXVL
+        print ("SVSTATE", bin(svstate.asint()))
 
         with Program(lst, bigendian=False) as program:
             sim = self.run_tst_program(program, svstate=svstate,