convert all test_caller*.py to work with pytest/unittest test discovery

[openpower-isa.git] / src / openpower / decoder / isa / test_caller_svp64_matrix.py

diff --git a/src/openpower/decoder/isa/test_caller_svp64_matrix.py b/src/openpower/decoder/isa/test_caller_svp64_matrix.py
index 99ca74df945a1189a07e2e3bf14ba06b06c5ec5d..051199c8b2e302379673a33e3da15eedcffda121 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_matrix.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_matrix.py
@@ -1,5 +1,5 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
 from openpower.decoder.isa.caller import ISACaller
@@ -15,7 +15,6 @@ from openpower.sv.trans.svp64 import SVP64Asm
 from openpower.consts import SVP64CROffs
 from copy import deepcopy
 from openpower.decoder.helpers import fp64toselectable
-from openpower.decoder.isafunctions.double2single import DOUBLE2SINGLE
 from functools import reduce
 import operator
 
@@ -28,14 +27,14 @@ class DecoderTestCase(FHDLTestCase):
 
     def test_sv_remap1(self):
         """>>> lst = ["svshape 2, 2, 3, 0, 0",
-                        "svremap 31, 1, 2, 3, 0, 0",
-                       "sv.fmadds 0.v, 8.v, 16.v, 0.v"
+                        "svremap 31, 1, 2, 3, 0, 0, 0",
+                       "sv.fmadds *0, *8, *16, *0"
                         ]
                 REMAP fmadds FRT, FRA, FRC, FRB
         """
         lst = SVP64Asm(["svshape 2, 2, 3, 0, 0",
-                        "svremap 31, 1, 2, 3, 0, 0",
-                       "sv.fmadds 0.v, 16.v, 32.v, 0.v"
+                        "svremap 31, 1, 2, 3, 0, 0, 0",
+                       "sv.fmadds *0, *16, *32, *0"
                         ])
         lst = list(lst)
 
@@ -76,15 +75,8 @@ class DecoderTestCase(FHDLTestCase):
             #print ("FFT", i, "in", a, b, "coeff", c, "mul",
             #       mul, "res", t, u)
 
-        # SVSTATE (in this case, VL=12, to cover all of matrix)
-        svstate = SVP64State()
-        svstate.vl[0:7] = 12 # VL
-        svstate.maxvl[0:7] = 12 # MAXVL
-        print ("SVSTATE", bin(svstate.spr.asint()))
-
         with Program(lst, bigendian=False) as program:
-            sim = self.run_tst_program(program, svstate=svstate,
-                                       initial_fprs=fprs)
+            sim = self.run_tst_program(program, initial_fprs=fprs)
             print ("spr svshape0", sim.spr['SVSHAPE0'])
             print ("    xdimsz", sim.spr['SVSHAPE0'].xdimsz)
             print ("    ydimsz", sim.spr['SVSHAPE0'].ydimsz)
@@ -101,14 +93,14 @@ class DecoderTestCase(FHDLTestCase):
 
     def test_sv_remap2(self):
         """>>> lst = ["svshape 5, 4, 3, 0, 0",
-                        "svremap 31, 1, 2, 3, 0, 0",
-                       "sv.fmadds 0.v, 8.v, 16.v, 0.v"
+                        "svremap 31, 1, 2, 3, 0, 0, 0",
+                       "sv.fmadds *0, *8, *16, *0"
                         ]
                 REMAP fmadds FRT, FRA, FRC, FRB
         """
         lst = SVP64Asm(["svshape 4, 3, 3, 0, 0",
-                        "svremap 31, 1, 2, 3, 0, 0",
-                       "sv.fmadds 0.v, 16.v, 32.v, 0.v"
+                        "svremap 31, 1, 2, 3, 0, 0, 0",
+                       "sv.fmadds *0, *16, *32, *0"
                         ])
         lst = list(lst)