convert all test_caller*.py to work with pytest/unittest test discovery

[openpower-isa.git] / src / openpower / decoder / isa / test_caller_svp64_matrix.py

diff --git a/src/openpower/decoder/isa/test_caller_svp64_matrix.py b/src/openpower/decoder/isa/test_caller_svp64_matrix.py
index c15479db9a36055166b6b023c7495f9ca3637333..051199c8b2e302379673a33e3da15eedcffda121 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_matrix.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_matrix.py
@@ -1,5 +1,5 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
 from openpower.decoder.isa.caller import ISACaller
@@ -28,13 +28,13 @@ class DecoderTestCase(FHDLTestCase):
     def test_sv_remap1(self):
         """>>> lst = ["svshape 2, 2, 3, 0, 0",
                         "svremap 31, 1, 2, 3, 0, 0, 0",
-                       "sv.fmadds 0.v, 8.v, 16.v, 0.v"
+                       "sv.fmadds *0, *8, *16, *0"
                         ]
                 REMAP fmadds FRT, FRA, FRC, FRB
         """
         lst = SVP64Asm(["svshape 2, 2, 3, 0, 0",
                         "svremap 31, 1, 2, 3, 0, 0, 0",
-                       "sv.fmadds 0.v, 16.v, 32.v, 0.v"
+                       "sv.fmadds *0, *16, *32, *0"
                         ])
         lst = list(lst)
 
@@ -93,14 +93,14 @@ class DecoderTestCase(FHDLTestCase):
 
     def test_sv_remap2(self):
         """>>> lst = ["svshape 5, 4, 3, 0, 0",
-                        "svremap 31, 1, 2, 3, 0, 0, 0, 0",
-                       "sv.fmadds 0.v, 8.v, 16.v, 0.v"
+                        "svremap 31, 1, 2, 3, 0, 0, 0",
+                       "sv.fmadds *0, *8, *16, *0"
                         ]
                 REMAP fmadds FRT, FRA, FRC, FRB
         """
         lst = SVP64Asm(["svshape 4, 3, 3, 0, 0",
-                        "svremap 31, 1, 2, 3, 0, 0, 0, 0",
-                       "sv.fmadds 0.v, 16.v, 32.v, 0.v"
+                        "svremap 31, 1, 2, 3, 0, 0, 0",
+                       "sv.fmadds *0, *16, *32, *0"
                         ])
         lst = list(lst)