sort out subvl unit test with expected results

[openpower-isa.git] / src / openpower / decoder / isa / test_caller_svp64_matrix.py

diff --git a/src/openpower/decoder/isa/test_caller_svp64_matrix.py b/src/openpower/decoder/isa/test_caller_svp64_matrix.py
index accbcd68dc7983f33bfa4a9a50d824b77a11911b..43f14c8e807d37b6c27a822002b5f02cb2b33662 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_matrix.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_matrix.py
@@ -15,7 +15,6 @@ from openpower.sv.trans.svp64 import SVP64Asm
 from openpower.consts import SVP64CROffs
 from copy import deepcopy
 from openpower.decoder.helpers import fp64toselectable
-from openpower.decoder.isafunctions.double2single import DOUBLE2SINGLE
 from functools import reduce
 import operator
 
@@ -28,14 +27,14 @@ class DecoderTestCase(FHDLTestCase):
 
     def test_sv_remap1(self):
         """>>> lst = ["svshape 2, 2, 3, 0, 0",
-                        "svremap 31, 1, 2, 3, 0, 0",
-                       "sv.fmadds 0.v, 8.v, 16.v, 0.v"
+                        "svremap 31, 1, 2, 3, 0, 0, 0",
+                       "sv.fmadds *0, *8, *16, *0"
                         ]
                 REMAP fmadds FRT, FRA, FRC, FRB
         """
         lst = SVP64Asm(["svshape 2, 2, 3, 0, 0",
-                        "svremap 31, 1, 2, 3, 0, 0",
-                       "sv.fmadds 0.v, 16.v, 32.v, 0.v"
+                        "svremap 31, 1, 2, 3, 0, 0, 0",
+                       "sv.fmadds *0, *16, *32, *0"
                         ])
         lst = list(lst)
 
@@ -94,14 +93,14 @@ class DecoderTestCase(FHDLTestCase):
 
     def test_sv_remap2(self):
         """>>> lst = ["svshape 5, 4, 3, 0, 0",
-                        "svremap 31, 1, 2, 3, 0, 0",
-                       "sv.fmadds 0.v, 8.v, 16.v, 0.v"
+                        "svremap 31, 1, 2, 3, 0, 0, 0",
+                       "sv.fmadds *0, *8, *16, *0"
                         ]
                 REMAP fmadds FRT, FRA, FRC, FRB
         """
         lst = SVP64Asm(["svshape 4, 3, 3, 0, 0",
-                        "svremap 31, 1, 2, 3, 0, 0",
-                       "sv.fmadds 0.v, 16.v, 32.v, 0.v"
+                        "svremap 31, 1, 2, 3, 0, 0, 0",
+                       "sv.fmadds *0, *16, *32, *0"
                         ])
         lst = list(lst)