from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
from nmutil.formaltest import FHDLTestCase
import unittest
from openpower.decoder.isa.caller import ISACaller
"addi 2, 0, 0x0008",
"addi 5, 0, 0x1234",
"addi 6, 0, 0x1235",
- "sv.stw 5.v, 0(1.v)",
- "sv.lwz 9.v, 0(1.v)"])
+ "sv.stw *5, 0(*1)",
+ "sv.lwz *9, 0(*1)"])
lst = list(lst)
# SVSTATE (in this case, VL=2)
svstate = SVP64State()
- svstate.vl[0:7] = 2 # VL
- svstate.maxvl[0:7] = 2 # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 2 # VL
+ svstate.maxvl = 2 # MAXVL
+ print ("SVSTATE", bin(svstate.asint()))
with Program(lst, bigendian=False) as program:
sim = self.run_tst_program(program, svstate=svstate)
# |
# dest r3=0b10 N Y
- isa = SVP64Asm(['sv.extsb/sm=~r3/dm=r3 5.v, 9.v'
+ isa = SVP64Asm(['sv.extsb/sm=~r3/dm=r3 *5, *9'
])
lst = list(isa)
print ("listing", lst)
initial_regs[10] = 0x90 # this gets skipped
# SVSTATE (in this case, VL=2)
svstate = SVP64State()
- svstate.vl[0:7] = 2 # VL
- svstate.maxvl[0:7] = 2 # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 2 # VL
+ svstate.maxvl = 2 # MAXVL
+ print ("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[5] = 0x0 # dest r3 is 0b10: skip
def test_sv_extsw_intpred_dz(self):
# extsb, integer twin-pred mask: dest is r3 (0b01), zeroing on dest
- isa = SVP64Asm(['sv.extsb/dm=r3/dz 5.v, 9.v'
+ isa = SVP64Asm(['sv.extsb/dm=r3/dz *5, *9'
])
lst = list(isa)
print ("listing", lst)
initial_regs[10] = 0x90 # this gets read but the output gets zero'd
# SVSTATE (in this case, VL=2)
svstate = SVP64State()
- svstate.vl[0:7] = 2 # VL
- svstate.maxvl[0:7] = 2 # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 2 # VL
+ svstate.maxvl = 2 # MAXVL
+ print ("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[5] = 0xffff_ffff_ffff_ff91 # dest r3 is 0b01: store
# adds, integer predicated mask r3=0b10
# 1 = 5 + 9 => not to be touched (skipped)
# 2 = 6 + 10 => 0x3334 = 0x2223+0x1111
- isa = SVP64Asm(['sv.add/m=r3 1.v, 5.v, 9.v'
+ # reg num 0 1 2 3 4 5 6 7 8 9 10 11
+ # src r3=0b10 N Y N Y
+ # | | | |
+ # +-------+ | add + |
+ # | +-------+ add --+
+ # | |
+ # dest r3=0b10 N Y
+ isa = SVP64Asm(['sv.add/m=r3 *1, *5, *9'
])
lst = list(isa)
print ("listing", lst)
initial_regs[6] = 0x2223
# SVSTATE (in this case, VL=2)
svstate = SVP64State()
- svstate.vl[0:7] = 2 # VL
- svstate.maxvl[0:7] = 2 # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 2 # VL
+ svstate.maxvl = 2 # MAXVL
+ print ("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[1] = 0xbeef
# adds, CR predicated mask CR4.eq = 1, CR5.eq = 0, invert (ne)
# 1 = 5 + 9 => not to be touched (skipped)
# 2 = 6 + 10 => 0x3334 = 0x2223+0x1111
- isa = SVP64Asm(['sv.add/m=ne 1.v, 5.v, 9.v'
+ isa = SVP64Asm(['sv.add/m=ne *1, *5, *9'
])
lst = list(isa)
print ("listing", lst)
initial_regs[6] = 0x2223
# SVSTATE (in this case, VL=2)
svstate = SVP64State()
- svstate.vl[0:7] = 2 # VL
- svstate.maxvl[0:7] = 2 # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 2 # VL
+ svstate.maxvl = 2 # MAXVL
+ print ("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[1] = 0xbeef
# | |
# dest always Y Y Y
- isa = SVP64Asm(['sv.extsb/sm=r3 5.v, 9.v'])
+ isa = SVP64Asm(['sv.extsb/sm=r3 *5, *9'])
lst = list(isa)
print("listing", lst)
initial_regs[11] = 0x92 # source r3 is 0b101 so this will be used
# SVSTATE (in this case, VL=3)
svstate = SVP64State()
- svstate.vl[0:7] = 3 # VL
- svstate.maxvl[0:7] = 3 # MAXVL
- print("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 3 # VL
+ svstate.maxvl = 3 # MAXVL
+ print("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[5] = 0xffff_ffff_ffff_ff90 # (from r9)
# | |
# dest r3=0b101 Y N Y
- isa = SVP64Asm(['sv.extsb/dm=r3 5.v, 9.v'])
+ isa = SVP64Asm(['sv.extsb/dm=r3 *5, *9'])
lst = list(isa)
print("listing", lst)
initial_regs[11] = 0x92 # the VL loop runs out before we can use it
# SVSTATE (in this case, VL=3)
svstate = SVP64State()
- svstate.vl[0:7] = 3 # VL
- svstate.maxvl[0:7] = 3 # MAXVL
- print("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 3 # VL
+ svstate.maxvl = 3 # MAXVL
+ print("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[5] = 0xffff_ffff_ffff_ff90 # 1st bit of r3 is 1
# |
# dest ~r3=0b010 N Y N
- isa = SVP64Asm(['sv.extsb/sm=r3/dm=~r3 5.v, 9.v'])
+ isa = SVP64Asm(['sv.extsb/sm=r3/dm=~r3 *5, *9'])
lst = list(isa)
print("listing", lst)
initial_regs[11] = 0x92 # VL loop runs out before we can use it
# SVSTATE (in this case, VL=3)
svstate = SVP64State()
- svstate.vl[0:7] = 3 # VL
- svstate.maxvl[0:7] = 3 # MAXVL
- print("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 3 # VL
+ svstate.maxvl = 3 # MAXVL
+ print("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[5] = 0x0 # dest ~r3 is 0b010: skip
# dest ~r3=0b1010 N Y N Y
# dststep=2 ^
- isa = SVP64Asm(['sv.extsb/sm=r3/dm=~r3 5.v, 9.v'])
+ isa = SVP64Asm(['sv.extsb/sm=r3/dm=~r3 *5, *9'])
lst = list(isa)
print("listing", lst)
# SVSTATE (in this case, VL=4)
svstate = SVP64State()
- svstate.vl[0:7] = 4 # VL
- svstate.maxvl[0:7] = 4 # MAXVL
+ svstate.vl = 4 # VL
+ svstate.maxvl = 4 # MAXVL
# set src/dest step on the middle of the loop
- svstate.srcstep[0:7] = 1
- svstate.dststep[0:7] = 2
- print("SVSTATE", bin(svstate.spr.asint()))
+ svstate.srcstep = 1
+ svstate.dststep = 2
+ print("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[5] = 0x0 # skip
# |
# dest r3=1: 1<<r3=0b010 N Y N
- isa = SVP64Asm(['sv.extsb/dm=1<<r3/sm=r30 5.v, 9.v'])
+ isa = SVP64Asm(['sv.extsb/dm=1<<r3/sm=r30 *5, *9'])
lst = list(isa)
print("listing", lst)
initial_regs[11] = 0x92 # 3rd bit of r30 is 1
# SVSTATE (in this case, VL=3)
svstate = SVP64State()
- svstate.vl[0:7] = 3 # VL
- svstate.maxvl[0:7] = 3 # MAXVL
- print("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 3 # VL
+ svstate.maxvl = 3 # MAXVL
+ print("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[5] = 0x0 # skip
# |
# dest r30=0b010 N Y N
- isa = SVP64Asm(['sv.extsb/sm=1<<r3/dm=r30 5.v, 9.v'])
+ isa = SVP64Asm(['sv.extsb/sm=1<<r3/dm=r30 *5, *9'])
lst = list(isa)
print("listing", lst)
initial_regs[11] = 0x92 # r3 is 2, so this will be used
# SVSTATE (in this case, VL=3)
svstate = SVP64State()
- svstate.vl[0:7] = 3 # VL
- svstate.maxvl[0:7] = 3 # MAXVL
- print("SVSTATE", bin(svstate.spr.asint()))
+ svstate.vl = 3 # VL
+ svstate.maxvl = 3 # MAXVL
+ print("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[5] = 0x0 # skip
# cr7.lt=1 N Y N Y
# dststep=2 ^
- isa = SVP64Asm(['sv.extsb/sm=eq/dm=lt 5.v, 9.v'])
+ isa = SVP64Asm(['sv.extsb/sm=eq/dm=lt *5, *9'])
lst = list(isa)
print("listing", lst)
cr.crl[7][CRFields.LT] = 1
# SVSTATE (in this case, VL=4)
svstate = SVP64State()
- svstate.vl[0:7] = 4 # VL
- svstate.maxvl[0:7] = 4 # MAXVL
+ svstate.vl = 4 # VL
+ svstate.maxvl = 4 # MAXVL
# set src/dest step on the middle of the loop
- svstate.srcstep[0:7] = 1
- svstate.dststep[0:7] = 2
- print("SVSTATE", bin(svstate.spr.asint()))
+ svstate.srcstep = 1
+ svstate.dststep = 2
+ print("SVSTATE", bin(svstate.asint()))
# copy before running
expected_regs = deepcopy(initial_regs)
expected_regs[5] = 0x0 # skip